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p/n:pm0887 mx10e8050i / major difference product default isp iap package clock mode mx10e8050ipc 44 pin pdip mx10e8050iqc 6 uart yes 44 pin plcc MX10E8050IUC 44 pin lqfp m x10e8050iaqc 6 i 2 c y e s 44 p i n p l c c 1 specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia feature rev. 1.6, mar. 28, 2005
2 p/n:pm0887 features - 80c51 cpu core - 3.0 ~ 3.6v voltage range - on-chip flash program memory with in-system programming ( isp ) - operating frequency up to 40mhz (12x), 20mhz(6x) - 64k bytes flash memory for code memory - 1280 bytes internal data ram - low power consumption - code and data memory expandable to 64k bytes - four 8 bit and one 4 bit general purpose i/o ports pin configurations - three standard 16-bit timers - in - application programming( iap ) capability - on-chip watch dog timer - four channel pwm outputs/4bit general purpose i/o ports ( plcc & lqfp only ) - uart - 7 interrupt sources with four priority level - 5 volt tolerant input - 400kb/s i 2 c - 6x / 12x clock mode plcc44 6140 7 17 39 29 18 28 pin function 1 p4.2/pwm2 2 p1.0/t2 3 p1.1/t2ex 4 p1.2 5 p1.3 6 p1.4 7 p1.5 8 p1.6/scl 9 p1.7/sda 10 rst 11 p3.0/rxd 12 p4.3/pwm3 13 p3.1/txd 14 p3.2/int0 15 p3.3/int1 pin function 16 p3.4/t0 17 p3.5/t1 18 p3.6/wr 19 p3.7/rd 20 xtal2 21 xtal1 22 v ss 23 p4.0/pwm0 24 p2.0/a8 25 p2.1/a9 26 p2.2/a10 27 p2.3/a11 28 p2.4/a12 29 p2.5/a13 30 p2.6/a14 pin function 31 p2.7/a15 32 psen 33 ale 34 p4.1/pwm1 35 ea 36 p0.7/ad7 37 p0.6/ad6 38 p0.5/ad5 39 p0.4/ad4 40 p0.3/ad3 41 p0.2/ad2 42 p0.1/ad1 43 p0.0/ad0 44 v cc specifications subject to change without notice, contact your sales representatives for the most update information. mx10e8050i / preliminary mx10e8050ia rev. 1.6, mar. 28, 2005
3 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 package type pdip plcc lqfp i/o symbol pin pin pin description i/o p0.0-p0.7 39-32 43-36 37-30 port:8-bit open drain bidirectional i/o port i/o p2.0-p2.7 21-28 24-31 18-25 port: 8-bit quasi-bidirectional i/o port with internal pull-up i/o p1.0-p1.7 1-8 2-9 40-44,1-3 port: 8-bit quasi-bidirectional i/o port with internal pull-up , except p1.6 and p1.7 i/o p3.0-p3.7 10-17 11,13-19 5,7-13 port: 8-bit quasi-bidirectional i/o port with internal pull-up i/o p4.0~p4.3/ na 23,34,1,12 17,28,39,6 4bit quasi-bidirectional i/o port or pwm pwm0~pwm3 i reset 9 10 4 reset input i vcc 40 44 38 positive power supply i vss 20 22 16 ground i xtal1 19 21 15 xtal connection input o xtal2 18 20 14 xtal connection output o psen 29 32 26 program store enable output o ale 30 33 27 address latch enable output i ea 31 35 29 external access input lqfp44 44 34 1 11 33 23 12 22 pin function 1 p1.5 2 p1.6/scl 3 p1.7/sda 4 rst 5 p3.0/rxd 6 p4.3/pwm3 7 p3.1/txd 8 p3.2/int0 9 p3.3/int1 10 p3.4/t0 11 p3.5/t1 12 p3.6/wr 13 p3.7/rd 14 xtal2 15 xtal1 pin function 16 v ss 17 p4.0/pwm0 18 p2.0/a8 19 p2.1/a9 20 p2.2/a10 21 p2.3/a11 22 p2.4/a12 23 p2.5/a13 24 p2.6/a14 25 p2.7/a15 26 psen 27 ale 28 p4.1/pwm1 29 ea 30 p0.7/ad7 pin function 31 p0.6/ad6 32 p0.5/ad5 33 p0.4/ad4 34 p0.3/ad3 35 p0.2/ad2 36 p0.1/ad1 37 p0.0/ad0 38 v cc 39 p4.2/pwm2 40 p1.0/t2 41 p1.1/t2ex 42 p1.2 43 p1.3 44 p1.4 pdip 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (t2) p1.0 (t2ex) p1.1 p1.2 p1.3 p1.4 p1.5 (scl)p1.6 (sda)p1.7 reset (rxd) p3.0 (txd)p3.1 (int0) p3.2 (int1) p3.3 (t0) p3.4 (t1) p3.5 (wr) p3.6 (rd) p3.7 xtal2 xtal1 vss 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea ale psen p2.7 (a15) p2.6 (a14) p2.5 (a13) p2.4 (a12) p2.3 (a11) p2.2 (a10) p2.1 (a9) p2.0 (a8) table. 1 pin description
4 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 mnemonic pin number type name and function pdip plcc lqfp v ss 20 22 16 i ground: 0 volt reference v cc 40 44 38 i power supply: this is the power supply voltage for normal, idle and power-down operation p0.0 ~ 0.7 39-32 43-36 37-30 i/o port 0: port 0 is an open drain, bi-directional i/o port. port 0 pins have 1s written to them float and can be used as high impedance inputs. port 0 is also the multiplexed low-order address and data bus during accessed to external program and data memory. in this application, it uses strong internal pull-ups when emitting 1s. p1.0~1.7 1-8 2-9 40-44 i/o port1: port 1 is an 8-bit bi-directional i/o port with internal 1-3 pull-ups. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. note that p1.6 and p1.7 are open drain pins for i 2 c function. alternate functions for port 1 include: 1 2 40 i/o t2(p1.0): timer/counter 2 external count input/clock out 2 3 41 i t2ex(p1.1): timer/counter 2 reload / capture / direction control 3 4 42 i sda (p1.7): data line for i 2 c 4 5 43 i/o scl (p1.6): clock line for i 2 c 5 6 44 i/o 6 7 1 i/o 7 8 2 i/o 8 9 3 i/o p2.0~2.7 21-28 24-31 18-25 i/o port 2 : port 2 is an 8-bit bi-directional i/o port with internal pull-ups. port2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally pulled low will source current because of the internal pull-ups. port 2 emits the high ordered address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application, it uses strong internal pull-ups when emitting 1s. during accesses to external data memory using 8-bit addresses (movx@r i ), port 2 emits the contents of p2 special `function register. p3.0~3.7 10-17 11, 5, i/o port 3: port 3 is an 8-bit bi-directional i/o port with internal
5 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 13-19 7-13 pull-ups. port 3 pins that have 1s written to them are pulled high with the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current because of the internal pull-ups. port 3 also serves the special features of mx10e8050i family, as listed below: 10 11 5 i rxd (p3.0) : serial input port 11 13 7 o txd (p3.1) : serial output port 12 14 8 i int0 (p3.2) : external interrupt 0 13 15 9 i int1 (p3.3) : external interrupt 1 14 16 10 i t0 (p3.4) : timer 0 external input 15 17 11 i t1 (p3.5) : timer 1 external input 16 18 12 o wr (p3.6) : external data memory write strobe 17 19 14 o rd (p3.7) : external data memory read strobe p4.0~p4.3 i/o port 4: port 4 is an 4-bit bi-directional i/o port with internal pull-ups. port 4 pins that have 1s written to them are pulled high with the internal pull-ups and can be used as inputs. as inputs, port 4 pins that are externally pulled low will source current because of the internal pull-ups. port 4 also serves the special features of mx10e8050i family, as listed below: p4.0 23 17 i pwm0 (p4.0) : pwm module output 0 p4.1 34 28 i pwm1 (p4.1) : pwm module output 1 p4.2 1 39 i pwm2 (p4.2) : pwm module output 2 p4.3 12 6 i pwm3 (p4.3) : pwm module output 3 rst 9 10 4 i reset : a high on this pin for eight machine cycles while the oscillator is running, reset the devices. ale 30 33 27 o address latch enable: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at constant rate of 1/6 the oscillator frequency in 12x clock mode. 1/3 the oscillator frequency in 6x clock mode, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. psen 29 32 26 o program strobe enable: the read strobe to external program memory. when executing code from external program memory, psen is activated twice each machine cycle., except the two psen activation are skipped during each access to external data memory. psen is not activated during fetch from internal program memory. ea 31 35 15 i external access enable/ programming supply voltage: ea must be external held low to enable the device to fetch code from external program memory locations 0000h and ffffh for 64 k devices. xtal 1 19 21 15 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal 2 18 20 14 o crystal 2: output from the inverting oscillator amplifier.
6 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 block diagram port 0 drivers port 4 drivers port 0 latch port 4 latch acc psw tmp2 port 1 latch port 1 drivers p1.0-p1.7 xtal2 xtal1 osc. i2c tmp1 alu b register timing and control ram pwm vcc vss ram addr. register instruction register port 2 latch stack pointer rom port 2 drivers buffer dptr program addr. register t0/t1/t2 sfrs timers port 3 latch port 3 drivers input filter output stage pc incrementer program counter p0.0-p0.7 p4.0-p4.3 p2.0-p2.7 p3.0-p3.7 psen ale ea rst t3 watchdog timer
7 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 functional description general the mx10e8050i serial is a stand-alone high-performance and low power microcontroller designed for use in many applications which need code programmability. the flash eprom offers customers to program the device themselves. this feature increases the flexibility in many applications, not only in development stage, but also in mass production stage. in addition to the 80c51 standard functions, the mx10e8050i serial provides a number of dedicated hardware functions. mx10e8050i serial is a control-oriented cpu with on-chip program and data memory. it can execute program with internal memory up to 64k bytes. mx10e8050i serial has two software selectable modes of reduced activity for power reduction idle, and power-down. the idle mode freezes the cpu while allowing the ram, timers, serial ports, interrupt system and other peripherals to continue functioning. the power-down mode saves the ram contents but freezes the oscillator causing all other chip functions to be inoperative. power-down mode can be terminated by an external reset ,and in addition , by either of the two external interrupts can be terminated as the power down mode does. memory organization the central processing unit (cpu) manipulates operands in three memory spaces; these are the 256 bytes internal data memory (ram), 1k byte auxiliary data memory (aux-ram) and 64k byte internal mtp program memory ( flash rom ). program memory the program memory address space of the mx10e8050i serial comprises an internal and an external memory space. the mx10e8050i serial has 64k byte of program memory on-chip. program protection if the user choose to set security lock in mtp memory, the program content is protected from reading out of chip. internal data memory the internal data memory is divided into three physically separated parts: 256 byte of ram, 1k bytes of aux-ram, and 128 bytes special function register area (sfr). these parts can be addressed as follows (see fig.1 and table. 2) - ram 0 to 127 can be addressed directly and indirectly as in the 80c51. address pointers are r0 and r1 of the selected register bank. - ram 128 to 255 can only be addressed indirectly . address pointers are r0 and r1 of the selected register bank. - aux-ram 0 to 1023 is indirectly addressable as the external data memory locations 0 to 1023 by the movx instructions. address pointers are r0 and r1 of the selected register bank and dptr. sfrs can only be addressed directly in the address range from 128 to 255.
8 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 table. 2 internal data memory access location addressed ram 0 to 127 direct and indirect ram 128 to 255 indirect only aux-ram 0 to 1023 indirect only with movx special function register (sfr) 128 to 255 direct only fig. 1 shows the internal memory address space. table 3 shows the special function register (sfr) memory map. location 0 to 31 at the lower ram area can be devided into four 8-bit register banks. only one of these banks may be enabled at a time. the next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations. the stack can be located anywhere in the internal 256 byte ram. the stack depth is only limited by the available internal ram space of 256 bytes. all registers except the program counter and the four 8-byte register banks reside in the sfr address space. five methods to access memory space are as floww : - register - direct - register-indirect - immediate - base-register plus index-register-indirect. the first three methods can be used for addressing destination operands. most instructions have a 'destination / source' field that specifies the data type, addressing methods and operands involved. for operations other than movs, the destination operand is also a source operand. access to memory addresses is as follows: - register in one of the four 8-byte register banks through direct or register-indirect addressing. - 256 bytes of internal ram through direct or register-indirect addressing. bytes 0-127 of internal ram may be only be addressed indirectly as data ram. - sfr through direct addressing at address location 128-255. fig.1 internal program and data memory address space overlapped space with different access schemes flash memory 64k 255 127 main ram sfrs aux-ram 0 0 1023 internal program memory internal data memory indirect only direct and indirect sfrs direct only auxiliary ram through movx access
9 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 table. 3 sfr register map high nibble of sfr address low 8 9 a b c d e f 0 p0% p1% p2% p3% p4% psw% acc% b% 11111111 11111111 11111111 11111111 11111111 00000000 00000000 00000000 1sp pwmc 00000111 10000000 2 dpl auxr1 00000000 00000000 3 dph pwmp3 00000000 00000000 4 fmcon pwm2 00000001 00000000 5 fmdata pwm3 00000000 00000000 6 pwmp2 00000000 7 pcon iph 00000000 00000000 8 tcon% scon% ie% ip% t2con% s1con pdcon 00000000 00000000 00000000 00000000 00000000 00000000 00000000 9 tmod sbuf saddr saden t2mod s1sta 00000000 xxx xxxxx 00000000 00000000 11111110 11111000 a tl0 rcap2l s1dat 00000000 00000000 00000000 b tl1 rcap2h s1adr ebtcon pwmp1 00000000 00000000 00000000 xxxxxx1x 00000000 c th0 tl2 pwm0 00000000 00000000 00000000 d th1 th2 pwm1 00000000 00000000 00000000 e auxr pwmp0 00000000 00000000 f t3 11111111 notes : % = bit addressable register x = undefined
10 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 acc accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h auxr auxiliary 8eh - - - - - - extram ao 00000000b auxr1 auxiliary1 a2h - - enboot - - 0 - dps 00000000b b b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h dptr data pointer(2-byte) data pointer high dph data pointer low 83h 00h dpl 82h 00h ebtcon ena ble t3 ebh eb xxxxxx1xb fmcon flash control e4h pparam pale pceb poeb pweb - - preadyb 00000001b fmdata flash data e5h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000b af ae ad ac ab aa a9 a8 ie interrupt enable a8h ea et2 es1 es et1 ex1 et0 ex0 00000000b bf be bd bc bb ba b9 b8 ip interrupt priority b8h - pt2 ps1 ps pt1 px1 pt0 px0 x0000000b b7 b6 b5 b4 b3 b2 b1 b0 iph interrupt priority b7h - pt2h ps1h psh pt1h px1h pt0h px0h x0000000b high 87 86 85 84 83 82 81 80 p0 port 0 80h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ffh 97 96 95 94 93 92 91 90 p1 port 1 90h p17 p16 p15 p14 p13 p12 p11 p10 ffh a7 a6 a5 a4 a3 a2 a1 a0 p2 port 2 a0h ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ffh b7 b6 b5 b4 b3 b2 b1 b0 p3 port 3 b0h rd wr t1 t0 int1 int0 txd rxd ffh c3 c2 c1 c0 p4 port4 c0h - - - - pwm3 pwm2 pwm1 pwm0 fh pcon power control 87h smod1 smod0 - wle gf1 gf2 pd idl 00xx0000b pdcon rom enable code f8h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000b d7 d6 d5 d4 d3 d2 d1 d0 psw program status word d0h cy ac f0 rs1 rs0 ov - p 000000x0b pwmc pwm control f1h pwmd dscb pwm3e pwm2e dsca pwm1e pwm0e 1000x000b pwmp0 prescaler vector 0 feh pwmp pwmp pwmp pwmp pwmp pwmp pwmp pwmp 00000000b 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 pwmp1 prescaler vector 1 fbh pwmp pwmp pwmp pwmp pwmp pwmp pwmp pwmp 00000000b 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 pwmp2 prescaler vector 2 f6h pwmp pwmp pwmp pwmp pwmp pwmp pwmp pwmp 00000000b 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 pwmp3 prescaler vector 3 f3h pwmp pwmp pwmp pwmp pwmp pwmp pwmp pwmp 00000000b special function registers symbol description direct bit address, symbol, or alternative port function reset address msb lsb function
11 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0 pwm0 pwm0 ratio fch pwm pwm pwm pwm pwm pwm pwm pwm 00000000b 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 pwm1 pwm1 ratio fdh pwm pwm pwm pwm pwm pwm pwm pwm 00000000b 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 pwm2 pwm2 ratio f4h pwm pwm pwm pwm pwm pwm pwm pwm 00000000b 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 pwm3 pwm3 ratio f5h pwm pwm pwm pwm pwm pwm pwm pwm 00000000b 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0 racap2h timer 2 capture high cbh 00h racap2l timer 2 capture low cah 00h saddr slave address a9h 00h saden slave address mask b9h 00h sbuf serial data buffer 99h xxxxxxxxb 9f 9e 9d 9c 9b 9a 99 98 scon serial control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00h sp stack pointer 81h 07h df de dd dc db da d9 d8 s1con i 2 c control d8h cr2 ens1 sta sto si aa cr1 cr0 00h s1sta i 2 c status d9h s1sta.7 s1sta.6 s1sta.5 s1sta.4 s1sta.3 00h s1dat i 2 c data dah s1dat.7 s1dat.6 s1dat.5 s1dat.4 s1dat.3 s1dat.2 s1dat.1 s1dat.0 00h s1adr i 2 c address dbh s1adr.7 s1adr.6 s1adr.5 s1adr.4 s1adr.3 s1adr.2 s1adr.1 gc 00h tcon timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h cf ce cd cc cb ca c9 c8 t2con timer 2 control c8h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl 00h t2mod timer 2 mode control c9h ------t2oe dcen xxxxxx00b th0 timer high 0 8ch 00h th1 timer high 1 8dh 00h th2 timer high 2 cdh 00h tl0 timer low 0 8ah 00h tl1 timer low 1 8bh 00h tl2 timer low 2 cch 00h tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00h t3 timer 3 ffh ffh
12 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 auxr (8eh) extram a0 - extram : external ram select switch. set 1 to select (movx) the external ram directly. default is 0 to switch (movx) to external ram only when the a ddress is larger than 1k. - ao : turn off ale output in internal execution mode. ( 1 : turn off ) ( 0 : turn on ) watchdog timer/wdt/t3 (ffh) - wdt consists of an 11-bit prescaler and an 8-bit timer formed by sfr t3. ebtcon (ebh) /ew - /ew: after reset, /ew bit is set, and wdt is disable. power control register/pcon (87h) smod1 smod0 x wle gf1 gf0 pd idl - smod1: double baud rate bit for uart. - smod0: frame error detection bit. - wle: watchdog load enable. this flag must be set prior to loading wdt and is cleared when wdt is loaded. - gf1/gf0: general-purpose flag bit. - pd: power-down bit. setting it activates power-down mode. - idl: idle mode bit. setting it activates idle mode. - the cpu & peripheral status during 2 power saving mode: idle mode pow er-down mode cpu off off int,timer. on off oscillator ckt on off
13 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 i/o facilities mx10e8050i serial has one 8 bits port, port 0, which is open drain, three 8 bits ports, port1/2/3 and a four-bits port port 4 . they are quasi bi-directional ports except p1.6 and p1.7. these five ports are fully compatible to standard 80c51's port 0/1/2/3/4. - port3: pins can be configured individually to provide: external interrupt inputs (external interrupt 0/1); external inputs for timer/ counter 0 and timer /counter1, and uart receive / transmit. - port 1.6, port 1.7 : pins are used to be i 2 c clock and data i/o, which are open drain port pins which are not used for alternate functions may be used as normal bidirectional i/o pins. the generation or use of a port 1 or port 3 pin as an alternate function is carried out automatically by writing the associated sfr bit with proper value. i/o buffers in the mx10e8050i (ports 1,2,3,4) 2 oscillator penods strong pull-up p1 n p2 input buffer from port latch input data read port pin o p3 +3v i/o port 1,2,3,4 exclude p1.6,p1.7
14 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 timer/counter mx10e8050i serial timer/counter 0 and 1 are fully compatible to standard 80c51's. the mx10e8050i serial contains two 16-bit timer/counters, timer 0 and timer 1. timer 0 and timer 1 may be programmed to carry out the following functions: - measure time intervals and pulse durations - count events - generate interrupt requests. timer 0 and timer 1 timers 0 and 1 each have a control bit in tmod sfr that selects the timer or counter function of the corresponding timer. in the timer function, the register is incremented every machine cycle. thus, one can think of it as counting machine cycles. since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. in the counter function, the register is incremented in response to a high-to-low transition at the corresponding samples, when the transition shows a high in one cycle and a low in the next cycle, the counter is incremented. thus, it takes two machine cycles (24 oscillator periods) to recognize a high-to-low transition. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. timer 0 and timer 1 can be programmed independently to operate in one of four modes (refer to table 5) : - mode 0 : 8-bit timer/counter with devided-by-32 prescaler - mode 1 : 16-bit timer/counter - mode 2 : 8-bit timer/counter with automatic reload - mode 3 : timer 0 :one 8-bit timer/counter and one 8-bits timer. timer 1 :stopped. when timer 0 is in mode 3, timer 1 can be programmed to operate in modes 0, 1 or 2 but cannot set an interrupt request flag and generate an interrupt. however, the overflow from timer 1 can be used to pulse the serial port transmission-rgate generator. with a 16 mhz crystal, the counting frequency of these timer/counters is as follows: - in the timer function, the timer is incremented at a frequency of 1.33 mhz (oscillator frequency divided by 12). - in the counter function, the frequency handling range for external inputs is 0 hz to 0.66 mhz (oscillator frequency divided by 24). both internal and external inputs can be gated to the timer by a second external source for directly measuring pulse duration. the timers are started and stopped under software control. each one sets its interrupt request flag when it overflows from all logic 1's to all logic 0's (respectively, the automatic reload value), with the exception of mode 3 as previously described. tmod : timer/counter mode control register this register is located at address 89h. table. 4 tmod sfr (89h) 765 43210 gate c/ t m1 m0 gate c/ t m1 m0 (msb) (lsb) timer 1 timer 0 keep the above table with the following table
15 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 table. 5 description of tmod bits mnemonic position function timer 1 gate tmod.7 ti mer 1 gating control : when set, timer/counter '1' is enabled only while 'int1' pin is high and 'tr1' control bit is set. when cleared, timer/counter '1' is enabled whenever 'tr1' control bit is set. c/t tmod.6 ti mer or counter selector: cleared for timer operation (input from internal system clock). set for counter operation (input from 't1' input pin). m1 tmod.5 operation mode: see table 6. m0 tmod.4 operation mode: see table 6. timer 0 gate tmod.3 timer 0 gating control: when set, timer/counter '0' is enabled only while 'int0' pin is high and 'tr0' control bit is set. when cleared, timer/counter '0' is enabled whenever 'tr0' control bit is set. c/t tmod.2 ti mer or counter selector: cleared for timer operation (input from internal system clock). set for counter operation (input from 't0' input pin). m1 tmod.1 operation mode: see table 6. m0 tmod.0 operation mode: see table 6. table. 6 tmod m1 and m0 operating modes m1 m0 function 0 0 8-bit timer/counter : 'thx' with 5-bit prescaler. 0 1 16-bit timer/counter : 'thx' and 'tlx' are cascaded, there is no prescaler. 1 0 8-bit autoload timer/counter : 'thx' holds a value which is to be reloaded into 'tlx' each time it overflows. 1 1 timer 0: tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8- bit timer controlled by timer 1 control bits. 1 1 timer 1 : timer/counter 1 stopped. tcon : timer/counter control register this register is located at address 88h. notes : symbol description direct bit address, symbol, or alternative port function reset address msb lsb function tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00h
16 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 table. 8 description of tcon bits mnemonic position function tf1 tcon.7 ti mer 1 overflow flag : set by hardware on timer/counter overflow. cleared when interrupt is processed. tr1 tcon.6 ti mer 1 control bit : set/cleared by software to turn timer/counter on/off. tf0 tcon.5 timer 0 overflow flag: set by hardware on timer/counter overflow. cleared when interrupt is processed. tr0 tcon.4 ti mer 0 control bit : set/cleared by software to turn timer/counter on/off. ie1 tcon.3 interrupt 1 edge flag: set by hardware when external interrupt is detected. cleared when interrupt is processed. it1 tcon.2 interrupt 1 type control bit : set/cleared by software to specify falling edge/low level triggered external interrupt. ie0 tocn.1 interrupt 0 edge flag: set by hardware when external interrupt is detected. cleared when interrupt is processed. it0 tocn.0 interrupt 0 type control bit: set/cleared by software tospecify falling edge/low level triggered external interrupt. table. 7 tcon sfr (88h) 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 (msb) (lsb) keep the above table with the following table
17 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 timer 2 operation timer 2 timer 2 is a 16-bit timer/counter which can operate as either an event timer or an event counter, as selected by c/ t2* in the special function register t2con (see figure 2). timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator, which are selected by bits in the t2con as shown in table 9. capture mode in the capture mode there are two options which are selected by bit exen2 in t2con. if exen2=0, then timer 2 is a 16-bit timer or counter (as selected by c/t2* in t2con) which, upon overflowing sets bit tf2, the timer 2 overflow bit. this bit can be used to generate an interrupt (by enabling the timer 2 interrupt bit in the ie register). if exen2= 1, timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2 like tf2 can generate an interrupt (which vectors to the same location as timer 2 overflow interrupt. the timer 2 interrupt service routine can interrogate tf2 and exf2 to determine which event caused the interrupt). the capture mode is illustrated in figure b (there is no reload value for tl2 and th2 in this mode. even when a capture event occurs from t2ex, the counter keeps on counting t2ex pin transitions or osc/6 pulses (osc/12 in 12 clock mode).). auto-reload mode ( up or down counter ) in the 16-bit auto-reload mode, timer 2 can be configured (as either a timer or counter [c/t2* in t2con]) then programmed to count up or down. the counting direction is determined by bit dcen (down counter enable) which is located in the t2mod register (see figure 4). when reset is applied the dcen=0 which means timer 2 will default to counting up. if dcen bit is set, timer 2 can count up or down depending on the value of the t2ex pin. figure 5 shows timer 2 which will count up automatically since dcen=0. in this mode there are two options selected by bit exen2 in t2con register. if exen2=0, then timer 2 counts up to 0ffffh and sets the tf2 (overflow flag) bit upon overflow. this causes the timer 2 registers to be reloaded with the 16-bit value in rcap2l and rcap2h. the values in rcap2l and rcap2h are preset by software means. if exen2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input t2ex. this transition also sets the exf2 bit. the timer 2 interrupt, if enabled, can be generated when either tf2 or exf2 are 1. in figure 6 dcen=1 which enables timer 2 to count up or down. this mode allows pin t2ex to control the direction of count. when a logic 1 is applied at pin t2ex timer 2 will count up. timer 2 will overflow at 0ffffh and set the tf2 flag, which can then generate an interrupt, if the interrupt is enabled. this timer overflow also causes the 16-bit value in rcap2l and rcap2h to be reloaded into the timer registers tl2 and th2. when a logic 0 is applied at pin t2ex this causes timer 2 to count down. the timer will underflow when tl2 and th2 become equal to the value stored in rcap2l and rcap2h. timer 2 underflow sets the tf2 flag and causes 0ffffh to be reloaded into the timer registers tl2 and th2. the external flag exf2 toggles when timer 2 underflows or overflows. this exf2 bit can be used as a 17th bit of resolution if needed. the exf2 flag does not generate an interrupt in this mode of operation.
18 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 (msb) (lsb) symbol position name and significance tf2 t2con.7 timer 2 overflow flag set by a timer 2 overflow and must be cleared by software. tf2 will not be set when either rclk or tclk = 1. exf2 t2con.6 timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. when timer 2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. exf2 does not cause an interrupt in up/down counter mode (dcen = 1). rclk t2con.5 receive clock flag. when set, causes the serial port to use timer 2 overflow pulses for its receive clock in modes 1 and 3. rclk = 0 causes timer 1 overflow to be used for the receive clock. tclk t2con.4 transmit clock flag. when set, causes the serial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. tclk = 0 causes timer 1 overflows to be used for the transmit clock. exen2 t2con.3 timer 2 external enable flag. when set, allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 t2con.2 start/stop control for timer 2. a logic 1 starts the timer. c/t2 t2con.1 timer or counter select. (timer 2) 0 = internal timer (osc/6 in 6 clock mode or osc/12 in 12 clock mode) 1 = external event counter (falling edge triggered). cp/rl2 t2con.0 capture/reload flag. when set, captures will occur on negative transitions at t2ex if exen2 = 1. when cleared, auto-reloads will occur either with timer 2 overflows or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to auto-reload on timer 2 overflow. tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 figure 2. timer / counter 2 (t2con) control register table 9 : timer 2 operation modes rclk + tclk cp / rl2 tr2 mode 0 0 1 16-bit auto-reload 0 1 1 16-bit capture 1 x 1 baud rate generator x x 0 ( off )
19 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 not bit addressable symbol function - not implemented, reserved for future use.* dcen down count enable bit. when set, this allows timer 2 to be configured as an up/down counter. t2oe timer 2 output enable bit. 76543210 * user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reser ved bit is indeterminate. bit t2mod address = 0c9h reset value = xxxx xx00b dcen t2oe osc n* c/t2 = 0 c/t2 = 1 tr2 control tl2 (8-bits) th2 (8-bits) tf2 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector t2 pin capture * n = 12 in 12 clock mode. n = 6 in 6 clock mode. figure 3 : timer 2 in capture mode figure 4 : timer 2 mode (t2mod) control register
20 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 osc n* c/t2 = 0 c/t2 = 1 tr2 control tl2 (8-bits) th2 (8-bits) tf2 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector t2 pin reload * n = 12 in 12 clock mode. n = 6 in 6 clock mode. n* c/t2 = 0 c/t2 = 1 tl2 th2 tr2 control t2 pin ffh ffh rcap2l rcap2h (up counting reload value) t2ex pin tf2 interrupt count direction 1 = up 0 = down exf2 overflow (down counting reload value) toggle osc * n = 12 in 12 clock mode. n = 6 in 6 clock mode. figure 5 : timer 2 in auto-reload mode (dcen = 0) figure 6 : timer 2 auto-reload mode (dcen = 1)
21 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 table 10 : timer 2 generated commonly used baud rates baud rate timer 2 12 clock mode osc freq rcap2h rcap2l 375 k 12 mhz ff ff 9.6 k 12 mhz ff d9 2.8 k 12 mhz ff b2 2.4 k 12 mhz ff 64 1.2 k 12 mhz fe c8 300 12 mhz fb 1e 110 12 mhz f2 af 300 6 mhz fd 8f 110 6 mhz f9 57 baud rate generator mode bits tclk and / or rclk in t2con (table 10) allow the serial port transmit and receive baud rates to be derived from either timer 1 or timer 2. when tclk = 0, timer 1 is used as the serial port transmit baud rate generator. when tclk = 1, timer 2 is used as the serial port transmit baud rate generator. rclk has the same effect for the serial port receive baud rate. with there two bits, the serial port can have different receive and transmit baud rates - one generated by timer1, the other by timer2. figure 7 shows the timer2 in baud rate generation mode. the baud rate generation mode is like the auto-reload mode, in that a rollover in th2 causes the timer 2 registers to be reloaded with the 16-bit value in registers rcap2h and rcap2l, which are preset by software. the baud rates in modes 1 and 3 are determined by timer 2's overflow rate given below : modes 1 and 3 baud rates = timer 2 overflow rate 16 c/t2 = 0 c/t2 = 1 tr2 control tl2 (8-bits) th2 (8-bits) 16 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector t2 pin reload 2 "0" "0" "0" rx clock 16 tx clock "1" "1" "1" timer 1 overflow note availability of additional external interrupt. smod rclk tclk figure 7. timer 2 in baud rate generator mode osc n* * n = 2 in 12 clock mode. n = 1 in 6 clock mode.
22 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 where : (rcap2h, rcap2l) = the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. the timer 2 as a baud rate generator mode shown in figure7, is valid only if rclk and / or tclk = 1in t2con register. note that a rollover in th2 does not set tf2, and will not generate an interrupt. thus, the timer 2 interrupt does not have to be disabled when timer 2 is in the baudrate generator mode. also if the exen2 (t2 external enable flag) is set, a 1-to-0 transition in t2ex (timer / counter 2 trigger input) will set exf2 (t2 external flag) but will not cause a reload from (rcap2h, rcap2l) to (th2, tl2). therefore when timer 2 is in use as a baud rate generator, t2ex can be used as an additional external interrupt, if needed. when timer 2 is in the baud rate generator mode, one should not try to read or write th2 and tl2. as a baud rate generator, timer 2 is accurate. the rcap2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and / or reload errors. the timer should be turned off (clear tr2) before accessing the timer 2 or rcap2 registers. table 10 shows commonly used baud rates and how they can be obtained from timer 2. summary of baud rate equations timer 2 is in baud rate generating mode. if timer 2 is being clocked through pin t2(p1.0) the baud rate is : baud rate = timer 2 overflow rate 16 if timer 2 is being clocked internally, the baud rate is : baud rate = f osc [ n * x [65536 - (rcap2h, rcap2l) ] ] *n = 32 in 12 clock mode or 16 in 6 clock mode where f osc = oscillator frequency to obtain the reload value for rcap2h and rcap2l, the above equation can be rewritten as : rcap2h, rcap2l = 65536 - ( ) f osc n * x baud rate timer / counter 2 set-up except for the baud rate generator mode, the values given for t2con do not include the setting of the tr2 bit. therefore, bit tr2 must be set, separately, to turn the timer on. see table 11 for set-up of timer 2 as a timer. also see table 12 for set-up of timer 2 as a counter. the timer can be configured for either "timer" or "counter" operation. in many applications, it is configured for "timer" operation ( c/t 2* = 0). timer operation is different for timer 2 when it is being used as a baud rate generator. usually, as a timer it would increment every machine cycle ( i.e., 1/6 the oscillator frequency in 6 clock mode, 1/ 12 the oscillator frequency in 12 clock mode). as a baud rate generator, it increments at the oscillator frequency in 6 clock mode (osc/2 in 12 clock mode). thus the baud rate formula is as follows : modes 1 and 3 baud rates = oscillator frequency [ n * x [65536 - (rcap2h, rcap2l) ] ] *n = 32 in 12 clock mode or 16 in 6 clock mode
23 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 notes : 1. capture / reload occurs only on timer / counter overflow. 2. capture / reload occurs on timer / counter overflow and a 1-to-0 transition on t2ex (p1.1) pin except when timer 2 is used in the baud rate generatior mode. table 11 : timer 2 as a timer t2con mode i nternal control external control (note 1) (note 2) 16-bit auto-reload 00h 08h 16-bit capture 01h 09h baud rate generator receive and transmit same baud rate 34h 36h receive only 24h 26h transmit only 14h 16h table 12 : timer 2 as a counter t2con mode i nternal control external control (note 1) (note 2) 16-bit 02h 0ah auto-reload 03h 0bh
24 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 interrupt system the mx10e8050i serial contains a 7-source (2 external interrupts, timer 0, timer1, timer2, i 2 c and uart) with four priority levels interrupt structure. each external interrupts int0 and int1, can be either level-activated or transition-activated depending on bits it0 and it1 in tcon sfr. the flags that actually generate these interrupts are bits ie0, ie1 in tcon. when an external interrupt is generated, the corresponding request flag is cleared by the hardware where the service routine is vectored to, if the interrupt is transition-activated. if the interrupt is level-activated the external source has to hold the request active until the requested interrupt is actually generated. then it has to deactive the request before the interrupt service routine is completed, otherwise another interrupt will be generated. the timer 0 and timer 1 interrupts are generated by tf0 and tf1, which are set by a rollover in their respective timer/counter register (except for timer 0 in mode 3 of the serial interface). when a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to. ie : interrupt enable register this register is located at address a8h. table. 13 ie sfr (a8h) 76543210 ea et2 es1 es et1 ex1 et0 ex0 (msb) (lsb) keep the above table with the following table table. 14 description of ie bits mnemonic position function ea ie.7 disable all interrupt - low, all disabled. - high, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. et2 ie.6 enable / disable timer2 interrupt. - low, disabled - high, enabled es1 ie.5 enable / disable l 2 c interrupt. - low, disabled - high, enabled es ie.4 enable / disable uart interrupt. - low, disabled - high, enabled et1 ie.3 enable / disable timer1 overflow interrupt. ex1 ie.2 enable / disable external interrupt 1. - low, disabled - high, enabled et0 ie.1 enable / disable timer0 overflow interrupt. ex0 ie.0 enable / disable external interrupt 0. - low, disabled - high, enabled
25 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 ip : interrupt priority register this register is located at address b8h. table. 15 ip sfr (b8h) 76543210 - pt2 ps1 ps pt1 px1 pt0 px0 ( lsb ) keep the above table with the following table table. 16 description of ip bits mnemonic position function - ip.7 reserved pt2 ip.6 define timer2 interrupt priority level. - high, assign a high priority level. ps1 ip.5 define i 2 c interrupt priority level. - high, assign a high priority level. ps ip.4 define interrupt priority level of uart. pt1 ip.3 define timer1 overflow interrupt priority level. px1 ip.2 define external interrupt 1 interrupt priority level. - high, assign a high priority level. pt0 ip.1 define timer0 overflow interrupt priority level. px0 ip.0 define external interrupt 0 interrupt priority level. - high, assign a high priority level.
26 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 name priority within level vector address ie0 (highest) 1 0003h i 2 c 2 002bh tf0 3 000bh ie1 4 0013h tf1 5 001bh ri + ti 6 0023h tf2 + exf2 (lowest) 7 0033h iph : interrupt high priority register this register is located at address b7h. table. 17 iph sfr (b7h) 76543210 - pt2h ps1h psh pt1h px1h pt0h px0h ( lsb ) table. 18 description of iph bits mnemonic position function - iph.7 reserved pt2h iph.6 def ine timer2 interrupt priority level. - high, assign a high priority level. ps1h iph.5 define i 2 c interrupt priority level. - high, assign a high priority level. psh iph.4 define interrupt priority level of uart. pt1h iph.3 def ine timer1 overflow interrupt priority level. px1h iph.2 define external interrupt 1 interrupt priority level. - high, assign a high priority level. pt0h iph.1 def ine timer0 overflow interrupt priority level. px0h iph.0 define external interrupt 0 interrupt priority level. - high, assign a high priority level. keep the above table with the following table
27 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 oscillator characteristics xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier. the pins can be configured for use as an on-chip oscillator. to drive the device from an external clock source, xtal1 should be driven while xtal2 is left unconnected. there are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. however, minimum and maximum high and low times specified in the datasheet must be observed. reset a reset is accomplished by holding the rst pin high for at least two and half machine cycles (15 oscillator periods in 6-clock mode, or 30 oscillator periods in 12-clock mode), while the oscillator is running. to ensure a good power-on reset, the rst pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. at power-on, the voltage on v cc and rst must come up at the same time for a proper start-up. ports 1,2, and 3 will asynchronously be driven to their reset condition when a voltage above v ih (min.) is applied to rst. idle mode in idle mode, the cpu puts itself to sleep while all of the on-chip peripherals stay active. the instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. the cpu contents, the on-chip ram, and all of the special function registers remain intact during this mode. the idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. power_down mode in the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. the power-down mode can be terminated by a reset in the same way as in the 80c51 or in addition by one of two external interrupts, int0 or int1. a termination with an external interrupt does ont affect the internal data memory and does not affect the internal data memory and does not affect the special function registers. this makes it possible to exit power-down without changing the port output levels. to terminate the power-down mode with any external interrupt int0 or int1 must be switched to level-sensitive and must be enabled. the external interrupt input signal int0 and int1 must be kept low until the oscillator has restarted and stabilized. an instruction following the instruction that puts the device in the power-down mode will be executed. a reset generated by the watchdog timer terminates the power-down mode in the same way as an external reset, and only the contents of the on-chip ram are preserved. the control bits for the reduced power modes are in the special function register pcon. design considerations at power-on, the voltage on v cc and rst must come up at the same time for a proper start-up. when the idle mode is terminated by a hardware reset, the device normally resumes program exectution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. table 19 shows the state of i/o ports during low current operation modes.
28 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 table 19. external pin status during idle and power-down modes mode prog ram memory ale psen port0 port1 port2 port3 idle internal 1 1 data data data data idle external 1 1 float data address data power-down internal 0 0 data data data data power-down external 0 0 float data ff data
29 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 watchdog timer the watchdog timer (wdt) see fig.8 , consists of an 11-bit prescaler and an 8-bit timer formed by sfr t3. the timer is incremented every 1.5 ms, derived from the system clock frequency of 16 mhz by the following formula : f timer = f clk / (12 x (2048)). the 8-bit timer increments every 12 x 2048 cycles of the on-chip oscillator. when a timer overflow occurs, the microcontroller is reset. the internal reset signal is not inhibited when the external rst pin is kept 0 into high impedance, no matter if the xtal-clock is running or not. to prevent a system reset the timer must be reloaded in time by the application software. if the processor suffers a hardware / software malfunction, the software will fail to reload the timer. this failure will result in an overflow thus prevent the processor from running out of control. this time interval is determined by the 8-bit reload value that is written into register t3. watchdog time interval = [ 100 - t3 ] x 12 x 2048 / oscillator frequency (12x mode) [ 100 - t3 ] x 6 x 2048 / oscillator frequency ( 6x mode) the watch-dog timer can only be reloaded if the condition flag wle (sfr pcon bit 4) has been previously set high by software. at the moment the counter is loaded wle is automatically cleared. in the idle state the watchdog timer and reset circuitry remain active. the watchdog timer is controlled by the watchdog enable signal ew (sfr ebtcon bit 1). a low level enables the watchdog timer. a high level disable the watchdog timer. fig. 8 watchdog timer t3 internal bus to reset circuitry timer t3 (8-bit) load loaden internal bus wle pd loaden prescaler (11-bit) clear clear f clk /12 write t3 ew pcon. 4 pcon. 1
30 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 pulse width modulated outputs the mx10e8050i contains four pulse width modulated output channels. these channels generate pulses of program- mable length and interval. two kinds of user modes are available. one is to use two channels as a pair of pwm output with one prescaler and four channels as two pairs of pwm outputs with each own single prescaler. the operation thus is like two set of independently pwm modules. the repetition frequency is defined by an 8-bit prescaler, which supplies the clock for the counter. the prescaler and counter are common to the both pwm channels in each set. the 8-bit counter counts modulo 255, i.e., from 0 to 254 inclusive. the value of the 8-bit counter is compared to the contents of two registers: pwm0 and pwm1 or pwm2 and pwm3. provided the contents of either of these registers is greater than the counter value, the corresponding pwm0 or pwm1 or pwm2 or pwm3 output is set low. if the contents of these registers are equal to, or less than the counter value, the output will be high. the pulse-width-ratio is therefore defined by the contents of the registers pwm0 and pwm1 or pwm2 and pwm3. the pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments of 1/255. the other one operation is that to use four channels as four independently pwm outputs with each own prescaler. f pwm = f osc 2 x (1 + pwmp) x 255 this gives a repetition frequency range of 123hz to 31.4khz (f osc = 16mhz). at f osc = 24mhz, the frequency range is 184hz to 47.1khz. by loading the pwm registers with either 00h or ffh, the pwm channels will output a constant high or low level, respectively. since the 8-bit counter counts modulo 255, it can never actually reach the value of the pwm registers when they are loaded with ffh. when a compare register (pwm0 or pwm1 or pwm2 or pwm3) is loaded with a new value, the associated output is updated immediately. it does not have to wait until the end of the current counter period. every pwmn output pins are driven by push-pull drivers. these pins are not used for any other purpose. the pwm function is enabled by setting sfr pwmc. sfr pwmc also controls operational mode and enable out. after reset, p4.0 to p4.3 are used to as the pwm output.
31 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 pwm module prescaler frequency control register / pwmpx pwmpx.7 pwmpx.6 pwmpx.5 pwmpx.4 pwmpx.3 pwmpx.2 pwmpx.1 wmpx.0 pwmpx x = 0, 1, 2, or 3 pwmp0 0feh pwmp1 0fbh pwmp2 0f6h pwmp3 0f3h bit symbol fuction pwmpx.7-0 pwmpx.7-0 prescaler division factor = (pwmpx) + 1 pwm module pulse width register / pwmx pwmx.7 pwmx.6 pwmx.5 pwmx.4 pwmx.3 pwmx.2 pwmx.1 pwmx.0 pwmx x = 0, 1, 2, or 3 pwm0 0fch pwm1 0fdh pwm2 0f4h pwm3 0f5h bit symbol fuction pwmx.7-0 pwmx.7-0 low/high ration of pwmx signal = (pwmx) / [255 - (pwmx)]
32 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 fig. 9 functional diagram of pulse width modulated outputs internal bus pwm0/2 pwm 0/2 pwm1/3 pwm 1/3 prescale (pwmp 1/3) 8-bit comparator output buffer 8-bit counter prescale (pwmp 0/2) 1/2 f ckl 8-bit counter output buffer 8-bit comparator dsca/dscb = 1 internal bus pwm0/2 pwm 0/2 pwm1/3 pwm 1/3 (pwmp 2,3) 8-bit comparator output buffer 8-bit counter prescale (pwmp 0,1) 1/2 f ckl output buffer 8-bit comparator dsca/dscb = 0
33 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 uart enhanced uart in addition to the standard operation the uart can perform framing error detect by looking for missing stop bits, and automatic address recognition. the uart also fully supports multiprocessor communication as does the standard 80c51 uart. when used for framing error detect the uart looks for missing stop bits in the communication. a missing bit will set the fe bit in the scon register. the fe bit shares the scon.7 bit with sm0 and the function of scon.7 is determined by pcon.6 (smod0) (see figure 10). if smod0 is set then scon.7 functions as fe. scon.7 functions as sm0 when smod0 is cleared. when used as fe scon.7 can only be cleared by software. automatic address recognition automatic address recognition is a feature which allows the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminat- ing the need for the software to examine every serial address which passes by the serial port. this feature is enabled by setting the sm2 bit in scon. in the 9 bit uart modes, mode 2 and mode 3, the receive interrupt flag (ri) will be automatically set when the received byte contains e ither the given a ddress or the broadca st a ddress. the 9-bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. automatic address recogintion is shown in figure 12. the 8 bit mode is called mode 1. in this mode the ri flag will be set if sm2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a given or broadcast address. mode 0 is the shift register mode and sm2 is ignored. using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. two special function registers are used to def ine the slaves a ddress, saddr, and the address mask, saden. saden is used to define which bits in the saddr are to b used and which bits are dont care. the saden mask can be logically anded with the saddr to create the given address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others. the following examples will help to show the versatility of this scheme: slave 0 saddr = 1100 0000 saden = 1111 1101 given = 1100 00x0 slave 1 saddr = 1100 0000 saden = 1111 1110 given = 1100 000x in the above example saddr is the same and the saden data is used to differentiate between the two slaves. slave 0 requires a 0 in bit 0 and it ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. a unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 1100 0000. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:
34 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 slave 0 saddr = 1100 0000 saden = 1111 1001 given = 1100 0xx0 slave 1 saddr = 1110 0000 saden = 1111 1010 given = 1110 0x0x slave 2 saddr = 1110 0000 saden = 1111 1100 given = 1110 00xx in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. to select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by taking the logical or of saddr and saden. zeros in this result are trended as dont-cares. in most cases, interpreting the dont-cares as ones, the broadcast address will be ff hexadecimal. upon reset saddr (sfr address 0a9h) and saden (sfr address 0b9h) are leaded with 0s. this produces a given address of all dont cares as well as a broadcast address of all dont care s. this effe ctively disables the automatic addressing mode and allows the microcontroller to use standard 80c51 type uart drivers which do not make use of this feature.
35 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 scon address = 98h reset value = 0000 0000b sm0/fe sm1 sm2 ren tb8 rb8 tl rl bit addressable (smod0 = 0/1)* symbol function fe framing error bit. this bit is set by the receiver when an invalid stop bit is detected. the fe bit is not cleared by valid frames but should be cleared by software. the smod0 bit must be set to enable access to the fe bit. sm0 serial port mode bit 0, (smod0 must = 0 to access bit sm0) sm1 serial port mode bit 1 sm0 sm1 mode description baud rate** 0 0 0 shift register f osc /6 (6-clock mode) or f osc /12 (12-clock mode) 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /32 or f osc /16 (6-clock mode) or f osc /64 or f osc /32 (12-clock mode) 1 1 3 9-bit uart variable sm2 enables the automatic address recognition feature in modes 2 or 3. if sm2 = 1 then rl will not be set unless the received 9th data bit (rb8) is 1, indicating an address, and the received byte is a given or broadcast address. in mode 1, if sm2 = 1 then rl will not be activated unless a valid stop bit was received, and the received byte is a given or broadcast address. in mode 0, sm2 should be 0. ren enables serial reception. set by software to enable reception. clear by software to disable reception. tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 in modes 2 and 3, the 9th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. tl transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software. rl receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software. note: *smod0 is located at pcon6. **f osc = oscillator frequency bit: 76543210 figure 10. scon : serial port control register
36 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 smod1 smod0 pof lvf gf0 gf1 idl pcon (87h) sm0 / fe sm1 sm2 ren tb8 rb8 ti ri scon (98h) d0 d1 d2 d3 d4 d5 d6 d7 d8 stop bit data byte only in mode 2, 3 start bit set fe bit if stop bit is 0 (framing error) sm0 to uart mode control 0 : scon.7 = sm0 1 : scon.7 = fe sm0 sm1 sm2 ren tb8 rb8 ti ri scon (98h) d0 d1 d2 d3 d4 d5 d6 d7 d8 1 1 1 0 comparator 11 x received address d0 to d7 programmed address in uart mode 2 or mode 3 and sm2 = 1: interrupt if ren=1, rb8=1 and a received address o = a programmed address o when own address received, clear sm2 to receive data bytes when all data bytes have been received: set sm2 to wait for next address. figure 11. uart framing error detection figure 12. uart multiprocessor communication, automatic address recognition
37 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 serial i/o the mx10e8050i serial is equipped with two independent serial ports : sio0 and sio1. sio0 is a full duplex uart port and is identical to the 80c51 serial port. sio0 : sio0 is a full duplex serial i/o port identical to that on the 80c51. it's operation is the same, including the use of timer 1 as a baud rate generator. sio1, i 2 c serial i/o : the i 2 c bus uses two wires ( sda and scl ) to transfer information between devices connected to the bus. the main features of the bus are : - bidirectional data transfer between masters and slaves - multimaster bus ( no central master ) - arbitration between simultaneously transmitting masters without corruption of serial data on the bus - serial clock synchronization allows devices with different bit rates to communicate via one serial bus - serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer - the i 2 c bus may be used for test and diagnostic purposes the output latches of p1.6 and p1.7 must be set to logic 1 in order to enable sio1. the mx10e8050i serial on-chip i 2 c logic provides a serial interface that meets the i 2 c bus specification and supports all transfer modes ( other than the low-speed mode ) from and to the i 2 c bus. the sio1 logic handles bytes transfer autonomously. it also keeps track of serial transfers, and a status register ( s1sta ) reflects the status of sio1 and the i 2 c bus. the cpu interfaces to the i 2 c logic via the following four special function register : s1con ( sio1 control register ), s1sta ( sio1 status register ), s1dat ( sio1 data register ), and s1adr ( sio1 slave address register ). the sio1 logic interfaces to the external i 2 c bus via two port 1 pins : p1.6/scl ( serial clock line ) and p1.7/sda ( serial data line ). a typical i 2 c bus configuration is shown in figure 13, and figure 14 shows how a data transfer is accomplished on the bus. depending on the state of the direction bit ( r/w ), two types of data transfers are possible on the i 2 c bus: 1. data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. 2. data transfer from a slave transmitter to a master receiver. the first byte ( the slave address ) is transmitted by the master. the slave then returns an acknowledge bit. next follows the data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a "not acknowledge" is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released.
38 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 modes of operation: the on-chip sio1 logic may operate in the following four modes: 1. master transmitter mode: serial data output through p1.7/sda while p1.6/scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. in this case the data direction bit (r/w) will be logic 0, and we say that a w is transmitted. thus the first byte transmitted is sla+w. serial data is transmitted 8 bits at a time. after each byte is transmitted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. 2. master receiver mode: the first byte transmitted contains the slave address of the transmitting device (7 bits) and the data direction bit. in this case the data direction bit (r/w) will be logic 1, and we say that an r is tran smitted. thus the first byte transmitted is sla+r. serial data is received via p1.7/sda while p1.6/scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are output to indicate the beginning and end of a serial transfer. 3. slave receiver mode: serial data and the serial clock are received through p1.7/sda and p1.6/scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. 4. slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit will indicate that the transfer direction is reversed. serial data is transmitted via p1.7/sda while the serial clock is input through p1.6/scl. start and stop conditions are recognized as the beginning and end of a serial transfer. in a given application, sio1 may operate as a master and as a slave. in the slave mode, the sio1 hardware looks for its own slave address and the general call address. if one of these addresses is detected, an interrupt is requested. when the microcontroller wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. if bus arbitration is lost in the master mode, sio1 switches to the slave mode immediately and can detect its own slave address in the same serial transfer. sio1 implementation and operation: figure 15 shows how the on-chip i 2 c bus interface is implemented, and the following text describes the individual blocks. input filters and output stages the input filters have i 2 c compatible input levels. if the input voltage is less than 1.5v, the input logic level is interpreted as 0; if the input voltage is greater than 3.0v, the input logic level is interpreted as 1. input signals are synchronized with the internal clock (f osc /4), and spikes shorter than three oscillator periods are filtered out. the output stages consist of open drain transistors that can sink 3ma at v out < 0.4v. these open drain outputs do not have clamping diodes to v dd . thus, if the device is connected to the i 2 c bus and v dd is switched off, the i 2 c bus is not
39 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 affected. address register, s1adr this 8-bit special function register may be loaded with the 7-bit slave address (7 most significant bits) to which sio1 will respond when programmed as a slave transmitter or receiver. the lsb (gc) is used to enable general call address (00h) recognition. comparator the comparator compares the received 7-bit slave address with its own slave address (7 most significant bits in s1adr). it also compares the first received 8-bit byte with the general call address (00h). if an equality is found, the appropriate status bits are set and an interrupt is requested. shift register, s1dat this 8-bit special function register contains a byte of serial data to be transmitted or a byte which has just been received. data in s1dat is always shifted from right to left; the first bit to be transmitted is the msb (bit 7) and, after a byte has been received, the first bit of received data is located at the msb of s1dat. while data is being shifted out, data on the bus is simultaneously being shifted in; s1dat always contains the last byte present on the bus. thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in s1dat.
40 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 figure 14. data transfer on the i 2 c bus figure 13. typical i 2 c bus configuration v dd other device with i 2 c interface mx10e8050i / ia other device with i 2 c interface p1.7/sda p1.6/scl sda scl i 2 c bus r p r p scl start condition s sda p/s msb acknowledgment signal from receiver clock line held low while interrupts are serviced 1 2 7 8 9 1 2 38 ack 9 ack repeated if more bytes are transferred acknowledgment signal from receiver slave address r/w direction bit stop condition repeated start condition
41 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 figure 15. i 2 c bus serial interface block diagram f osc /4 internal bus address register comparator shift register control register status register arbitration & sync logic timing & control logic serial clock generator ack status decoder timer 1 overflow interrupt 8 8 8 8 s1sta status bits s1con s1dat input filter output stage p1.7 input filter output stage p1.6 p1.6/scl p1.7/sda s1adr
42 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 figure 17. serial clock synchronization figure 16. arbitration procedure ack 1. another device transmits identical serial data. sda 1 234 89 scl (1) (1) (2) (3) 2. another device overrules a logic 1 (dotted line) transmitted by sio1 (master) by pulling the sda line low. arbitration is lost, and sio1 enters the slave receiver mode. 3. sio1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted. sio1 will not generate clock pulses for the next byte. data on sda originates from the new master once it has won arbitration. (1) scl (3) (1) sda mark duration space duration (2) 1. another service pulls the scl line low before the sio1"mark" duration is complete. the serial clock generator is immediately reset and commences with the "space" duration by pulling scl low. 2. another device still pulls the scl line low after sio1 releases scl. the serial clock generator is forced into the wait state until the scl line is released. 3. the scl line is released, and the serial clock generator commences with the mark duration.
43 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 arbitration and synchronization logic in the master transmitter mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the i 2 c bus. if another device on the bus overrules a logic 1 and pulls the sda line low, arbitration is lost, and sio1 immediately changes from master transmitter to slave receiver. sio1 will continue to output clock pulses (on scl) until transmission of the current serial byte is complete. arbitration may also be lost in the master receiver mode. loss of arbitration in this mode can only occur while sio1 is returning a not acknowledge: (logic 1) to the bus. arbitration is lost when another device on the bus pulls this signal low. since this can occur only at the end of a serial byte, sio1 generates no further clock pulses. figure 16 shows the arbitration procedure. the synchronization logic will synchronize the serial clock generator with the clock pulses on the scl line from another device. if two or more master devices generate clock pulses, the mark duration is determined by the device that generates the shortest marks, and the spa ce duration is determined by the device that generates the longest spaces. figure 17 shows the synchronization procedure. a slave may stretch the space duration to slow down the bus master. the space duration may also be stretched for handshaking purposes. this can be done after each bit or after a complete byte transfer. sio1 will stretch the scl space duration after a byte has been transmitted or received and the acknowledge bit has been transferred. the serial interrupt flag (si) is set, and the stretching continues until the serial interrupt flag is cleared. serial clock generator this programmable clock pulse generator provides the scl clock pulses when sio1 is in the master transmitter or master receiver mode. it is switched off when sio1 is in a slave mode. the programmable output clock frequencies are: f osc /120, f osc /9600, and the timer 1 overflow rate divided by eight. the output clock pulses have a 50% duty cycle unless the clock generator is synchronized with other scl clock sources as described above. timing and control the timing and control logic generates the timing and control signals for serial byte handling. this logic block provides the shift pulses for s1dat, enables the comparator, generates and detects start and stop conditions, receives and transmits acknowledge bits, controls the master and slave modes, contains interrupt request logic, and monitors the i 2 c bus status. control register, s1con this 7-bit special function register is used by the microcontroller to control the following sio1 functions: start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition, and acknowledgment. status decoder and status register the status decoder takes all of the internal status bits and compresses them into a 5-bit code. this code is unique for each i 2 c bus status. the 5-bit code may be used to generate vector addresses for fast processing of the various service routines. each service routine processes a particular bus status. there are 26 possible bus states if all four modes of sio1 are used. the 5-bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set (by hardware) and remains stable until the interrupt flag is cleared by software. the three least significant bits of the status register are always zero. if the status code is used as a vector to service routines, then the routines are displaced by eight address locations. eight bytes of code is sufficient for most of the service routines (see the software example in this section). the four sio1 special function registers: the microcontroller interfaces to sio1 via four special function regis- ters. these four sfrs (s1adr, s1dat, s1con, and s1sta) are described individually in the following sections.
44 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 the address register, s1adr: the cpu can read from and write to this 8-bit, directly addressable sfr. s1adr is not affected by the sio1 hardware. the contents of this register are irrelevant when sio1 is in a master mode. in the slave modes, the seven most significant bits must be loaded with the microcontrollers own slave address, and, if the least significant bit is set, the general call address (00h) is recognized; otherwise it is ignored. s1adr (dbh) 76543210 xxxxxxx gc own slave address the most significant bit corresponds to the first bit received from the i 2 c bus after a start condition. a logic 1 in s1adr corresponds to a high level on the i 2 c bus, and a logic 0 corresponds to a low level on the bus. the data register, s1dat: s1dat contains a byte of serial data to be transmitted or a byte which has just been received. the cpu can read from and write to this 8-bit, directly addressable sfr while it is not in the process of shifting a byte. this occurs when sio1 is in a defined state and the serial interrupt flag is set. data in s1dat remains stable as long as si is set. data in s1dat is always shifted from right to left: the first bit to be transmitted is the msb (bit 7), and, after a byte has been received, the first bit of received data is located at the msb of s1dat. while data is being shifted out, data on the bus is simultaneously being shifted in; s1dat always contains the last data byte present on the bus. thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in s1dat. s1adr (dah) 76543210 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 shift direction sd7 - sd0: eight bits to be transmitted or just received. a logic 1 in s1dat corresponds to a high level on the i 2 c bus, and a logic 0 corresponds to a low level on the bus. serial data shifts through s1dat from right to left. figure 18 shows how data in s1dat is serially transferred to and from the sda line. s1dat and the ack flag form a 9-bit shift register which shifts in or shifts out an 8-bit byte, followed by an acknowl- edge bit. the ack flag is controlled by the sio1 hardware and cannot be accessed by the cpu. serial data is shifted through the ack flag into s1dat on the rising edges of serial clock pulses on the scl line. when a byte has been shifted into s1dat, the serial data is available in s1dat, and the acknowledge bit is returned by the control logic during the ninth clock pulse. serial data is shifted out from s1dat via a buffer (bsd7) on the falling edges of clock pulses on the scl line. when the cpu writes to s1dat, bsd7 is loaded with the content of s1dat.7, which is the first bit to be transmitted to the sda line (see figure 19). after nine serial clock pulses, the eight bits in s1dat will have been transmitted to the sda line, and the acknowledge bit will be present in ack. note that the eight transmitted bits are shifted back into s1dat.
45 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 figure 18. serial input/output configuration the control register, s1con: the cpu can read from and write to this 8-bit, directly addressable sfr. two bits are affected by the sio1 hardware: the si bit is set when a serial interrupt is requested, and the sto bit is cleared when a stop condition is present on the i 2 c bus. the sto bit is also clea red when ens1 = 0. s1con (d8h) 76543210 cr2 ens1 sta sto si a a cr1 cr0 ens1, the sio1 enable bit ens1 = 0: when ens1 is 0, the sda and scl outputs are in a high impedance state. sda and scl input signals are ignored, sio1 is in the not addressed slave state, and the sto bit in s1con is f orced to 0. no other bits are affected. p1.6 and p1.7 may be used as open drain i/o ports. ens1 = 1: when ens1 is 1, sio1 is ena bled. the p1.6 and p1.7 port latches must be set to logic 1. ens1 should not be used to temporarily release sio1 from the i 2 c bus since, when ens1 is reset, the i 2 c bus status is lost. the aa flag should be used instead (see description of the aa flag in the following text). in the following text, it is assumed that ens1 = 1. sta, the start flag sta = 1: when the sta bit is set to enter a master mode, the sio1 hardware checks the status of the i 2 c bus and generates a start condition if the bus is free. if the bus is not free, then sio1 waits for a stop condition (which will free the bus) and generates a start condition after a delay of a half clock period of the internal serial clock generator. if sta is set while sio1 is already in a master mode and one or more bytes are transmitted or received, sio1 transmits a repeated start condition. sta may be set at any time. sta may also be set when sio1 is an addressed slave. sta = 0: when the sta bit is reset, no start condition or repeated start condition will be generated. sto, the stop flag sto = 1: when the sto bit is set while sio1 is in a master mode, a stop condition is transmitted to the i 2 c bus. when the stop condition is detected on the bus, the sio1 hardware clears the sto flag. in a slave mode, the sto flag may be set to recover from an error condition. in this case, no stop condition is transmitted to the i 2 c bus. however, the sio1 hardware behaves as if a stop condition has been received and switches to the def ined not addre ssed slave rece iver mode. the sto flag is automatically cleared by hardware. internal bus 8 bsd7 s1dat ack scl sda shift pulses
46 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 if the sta and sto bits are both set, the a stop condition is transmitted to the i 2 c bus if sio1 is in a master mode (in a slave mode, sio1 generates an internal stop condition which is not transmitted). sio1 then transmits a start condition. sto = 0: when the sto bit is reset, no stop condition will be generated. si, the serial interrupt flag si = 1: w hen the si flag is set, then, if the ea and es1 (interrupt enable register) bits are also set, a serial interrupt is requested. si is set by hardware when one of 25 of the 26 possible sio1 states is entered. the only state that does not cause si to be set is state f8h, which indicates that no relevant state information is available. while si is set, the low period of the serial clock on the scl line is stretched, and the serial transfer is suspended. a high level on the scl line is unaffected by the serial interrupt flag. si must be reset by software. si = 0: when the si flag is reset, no serial interrupt is requested, and there is no stretching of the serial clock on the scl line. aa, the assert acknowledge flag aa = 1: if the aa flag is set, an acknowledge (low level to sda) will be returned during the acknowledge clock pulse on the scl line when: - the own slave addre ss has been received - the general call address has been received while the general call bit (gc) in s1adr is set - a data byte has been received while sio1 is in the master receiver mode - a data byte has been received while sio1 is in the addressed slave receiver mode aa = 0: if the aa flag is re set, a not acknowledge (high level to sda) will be returned during the acknowledge clock pulse on scl when: - a data has been received while sio1 is in the master receiver mode - a data byte has been received while sio1 is in the addressed slave receiver mode when sio1 is in the addressed slave transmitter mode, state c8h will be entered after the last serial is transmitted (see figure 23). when si is cleared, sio1 leaves state c8h, enters the not addressed slave receiver mode, and the sda line remains at a high level. in state c8h, the aa flag can be set again for future address recognition. when sio1 is in the not addressed slave mode, its own slave address and the general call address are ignored. consequently, no acknowledge is returned, and a serial interrupt is not requested. thus, sio1 can be temporarily released from the i 2 c bus while the bus status is monitored. while sio1 is released from the bus, start and stop conditions are detected, and serial data is shifted in. address recognition can be resumed at any time by setting the aa flag. if the aa flag is set when the parts own slave address or the general call address has been partly received, the address will be recognized at the end of the byte transmission. cr0, cr1, and cr2, the clock rate bits these three bits determine the serial clock frequency when sio1 is in a master mode. the various serial rates are shown in table 19. a 12.5khz bit rate may be used by devices that interface to the i 2 c bus via standard i/o port lines which are software driven and slow. 100khz is usually the maximum bit rate and can be derived from a 16mhz, 12mhz, or a 6mhz oscillator. a variable bit rate (0.5khz to 62.5khz) may also be used if timer 1 is not required for any other purpose while sio1 is in a master mode. the frequencies shown in table 19 are unimportant when sio1 is in a slave mode. in the slave modes, sio1 will automatically synchronize with any clock frequency up to 100khz.
47 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 the status register, s1sta: s1sta is an 8-bit read-only special function register. the three least significant bits are always zero. the five most significant bits contain the status code. there are 26 possible status codes. when s1sta contains f8h, no relevant state information is available and no serial interrupt is requested. all other s1sta values correspond to defined sio1 states. when each of these states is entered, a serial interrupt is requested (si = 1 ). a va lid status code is present in s1sta one machine cycle after si is set by hardware and is still present one machine cycle after si has been reset by software. more information on sio1 operating modes: the four operating modes are: - master transmitter - master receiver - slave receiver - slave transmitter data transfers in each mode of operation are shown in figures 20~28. these figures contain the following abbrevia- tions: abbreviation explanation s start condition sla 7-bit slave address r read bit (high level at sda) w write bit (low level at sda) a acknowledge bit (low level at sda) a not acknowledge bit (high level at sda) data 8-bit data byte p stop condition in figures 20~28, circles are used to indicate when the serial interrupt flag is set. the numbers in the circles show the status code held in the s1sta register. at these points, a service routine must be executed to continue or complete the serial transfer. these service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. when a serial interrupt routine is entered, the status code in s1sta is used to branch to the appropriate service routine. for each status code, the required software action and details of the following serial transfer are given in table 21~25. master transmitter mode: in the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see figure 20). before the master transmitter mode can be entered, s1con must be initialized as follows: s1con (d8h) 76543210 cr2 ens1 sta sto si a a cr1 cr0 bit rate bit rate 1000x cr0, cr1, and cr2 define the serial bit rate. ens1 must be set to logic 1 to enable sio1. if the aa bit is reset, sio1 will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus. in other words, if aa is reset, sio0 cannot enter a slave mode. sta, sto, and si must be reset. the master transmitter mode may now be entered by setting the sta bit using the setb instruction. the sio1 logic will now test the i 2 c bus and generate a start condition as soon as the bus becomes free. when a start condition is transmitted, the serial interrupt flag (si) is set, and the status code in the status register (s1sta) will be 08h. this status code must be used to vector to an interrupt service routine that loads s1dat with the slave address and the data direction bit (sla+w). the si bit in s1con must then be reset before the serial transfer can continue.
48 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 shift in sda scl d7 d6 d5 d4 d3 d2 d1 d0 a shift ack & s1dat ack (2) (2) (2) (2) (2) (2) (2) (2) a (2) (2) (2) (2) (2) (2) (2) (2) (1) (1) s1dat shift bsd7 bsd7 d7 d6 d5 d4 d3 d2 d1 d0 (3) loaded by the cpu (1) valid data in s1dat (2) shifting data in s1dat and ack (3) high level on sda shift out figure 19. shift-in and shift-out timing table 20 : serial clock rates bit frequency (khz) at f osc cr2 cr1 cr0 6mhz 12mhz 16mhz f osc divided by 0 0 0 23 47 63 256 0 0 1 27 54 71 224 0 1 0 31 63 83 192 0 1 1 37 75 100 160 1 0 0 6.25 12.5 17 960 1 0 1 50 100 - 120 1 1 0 100 - - 60 1 1 1 0.25<62.5 0.5<62.5 0.67<56 96x(256-reload value timer1) (reload value range:0-254 in mode2) when the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in s1sta are possible. there are 18h, 20h, or 38h for the master mode and also 68h, 78h, or b0h if the slave mode was enabled (aa = logic 1). the appropriate action to be taken for each of these status codes is detailed in table 21. after a repeated start condition (state 10h). sio1 may switch to the master receiver mode by loading s1dat with sla+r).
49 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 figure 20. format and states in the master transmitter mode s sla wa a data p s sla w a p a p 08h 18h 28h r 38h a or a other mst continues a or a other mst continues 38h 30h 20h 68h 78h 80h other mst continues a mt 10h to mst/rec mode entry = mr to corresponding states in slave mode successful transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus. see table 21. data
50 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 figure 21. format and states in the master receiver mode s sla data r a data p s sla r a p 08h 40h 50h w 38h a or a other mst continues other mst continues 38h 48h 68h 78h 80h other mst continues a mr 10h to mst/trx mode entry = mt to corresponding states in slave mode successful reception from a slave transmitter next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or acknowledge bit arbitration lost and addressed as slave n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus. see table 22. a data a 58h a a data
51 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 figure 22. format and states in the slave receiver mode s sla wa a data p or s a 60h 80h 68h reception of the own slave address and one or more data bytes all are acknowledged. last data byte received is not acknowledged arbitration lost as mst and addressed as slave reception of the general call address and one or more data bytes last data byte is not acknowledged arbitration lost as mst and addressed as slave by general call a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus. see table 23. data a sla data 80h a0h a 88h p or s general call a data p or s 70h 90h 78h a data 90h a0h a 98h p or s a a
52 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 figure 23. format and states of the slave transmitter mode master receiver mode: in the master receiver mode, a number of data bytes are received from a slave transmitter (see figure 21). the transfer is initialized as in the master transmitter mode. when the start condition has been transmitted, the interrupt service routine must load s1dat with the 7-bit slave address and the data direction bit (sla+r). the si bit in s1con must then be cleared before the serial transfer can continue. when the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in s1sta are possible. these are 40h, 48h, or 38h for the master mode and also 68h, 78h, or b0h if the slave mode was enabled (aa = logic 1). the appropriate action to be taken for each of these status codes is detailed in table 22. ens1, cr1, and cr0 are not affected by the serial transfer and are not referred to in table 22. after a repeated start condition (state 10h), sio1 may switch to the master transmitter mode by loading s1dat with sla+w. slave receiver mode: in the slave receiver mode, a number of data bytes are received from a master transmitter (see figure 22). to initiate the slave receiver mode, s1adr and s1con must be loaded as follows: s1adr (dbh) 76543210 xxxxxxx gc the upper 7 bits are the address to which sio1 will respond when addressed by a master. if the lsb (gc) is set, sio1 will respond to the general call address (00h); otherwise it ignores the general call address. s1con (d8h) 76543210 cr2 ens1 sta sto s i aa cr1 cr0 x10001xx own slave address s sla r a data p or s b0h a8h b8h reception of the own slave address and transmission of one or more data bytes a data a c0h n any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus. see table 24. data a all "1"s a a from master to slave from slave to master c8h p or s last data byte transmitted. switched to not addressed slave (aa bit in s1con = "0" arbitration loast as mst and addressed as slave
53 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 cr0, cr1, and cr2 do not affect sio1 in the slave mode. ens1 must be set to logic 1 to enable sio1. the aa bit must be set to enable sio1 to acknowledge its own slave address or the general call address. sta, sto, and si must be reset. when s1adr and s1con have been initialized, sio1 waits until it is addressed by its own slave address followed by the data direction bit which must be 0 (w) for sio1 to operate in the slave receiver mode. after its own slave address and the w bit have been received, the serial interrupt flag (i) is set and a valid status code can be read from s1sta. this status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in table 23. the slave receiver mode may also be entered if arbitration is lost while sio1 is in the master mode (see status 68h and 78h). if the aa bit is reset during a transfer, sio1 will return a not acknowledge (logic 1) to sda after the next received data byte. while aa is reset, sio1 does not respond to its own slave address or a general call address. however, the i 2 c bus is still monitored and address recognition may be resumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate sio1 from the i 2 c bus.
54 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 table 21 : master transmitter mode application software response status code status of the i 2 c bus and to s1con next action taken by sio1 hardware (s1sta) sio1 hardware to/from s1dat sta sto si aa 08h a start condition has been transmitted load sla+w x 0 0 x sla+w will be transmitted; ack bit will be received 10h a repeated start condition has been transmitted load sla+w or load sla+r x x 0 0 0 0 x x as above sla+w will be transmitted; sio1 will be switched to mst/rec mode 18h sla+w has been transmitted; ack has been received load data byte or no s1dat action or no s1dat action or no s1dat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted; ack bit will be received repeated start will be transmitted; stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset 20h sla+w has been transmitted; not ack has been received load data byte or no s1dat action or no s1dat action or no s1dat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted; ack bit will be received repeated start will be transmitted; stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset 28h data byte in s1dat has been transmitted; ack has been received load data byte or no s1dat action or no s1dat action or no s1dat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted; ack bit will be received repeated start will be transmitted; stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset 30h data byte in s1dat has been transmitted; not ack has been received load data byte or no s1dat action or no s1dat action or no s1dat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted; ack bit will be received repeated start will be transmitted; stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset 38h arbitration lost in sla+r/w or data bytes no s1dat action or no s1dat action 0 1 0 0 0 0 x x i 2 c bus will be released; not addressed slave will be entered a start condition will be transmitted when the bus becomes free
55 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 table 22 : master receiver mode status status of the application software response code i 2 c bus and to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware sta sto si aa 08h a start condition has been transmitted load sla+r x 0 0 x sla+r will be transmitted; ack bit will be received 10h a repeated start condition has been transmitted load sla+r or load sla+w x x 0 0 0 0 x x as above sla+w will be transmitted; sio1 will be switched to mst/trx mode 38h arbitration lost in not ack bit no s1dat action or no s1dat action 0 1 0 0 0 0 x x i 2 c bus will be released; sio1 will enter a slave mode a start condition will be transmitted when the bus becomes free 40h sla+r has been transmitted; ack has been received no s1dat action or no s1dat action 0 0 0 0 0 0 0 1 data byte will be received; not ack bit will be returned data byte will be received; ack bit will be returned 48h sla+r has been transmitted; not ack has been received no s1dat action or no s1dat action or no s1dat action 1 0 1 0 1 1 0 0 0 x x x repeated start condition will be transmitted stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset 50h data byte has been received; ack has been returned read data byte or read data byte 0 0 0 0 0 0 0 1 data byte will be received; not ack bit will be returned data byte will be received; ack bit will be returned 58h data byte has been received; not ack has been returned read data byte or read data byte or read data byte 1 0 1 0 1 1 0 0 0 x x x repeated start condition will be transmitted stop condition will be transmitted; sto flag will be reset stop condition followed by a start condition will be transmitted; sto flag will be reset
56 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 table 23 : slave receiver mode status status of the application software response code i 2 c bus and to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware sta sto si aa 60h own sla+w has been received; ack has been returned no s1dat action or no s1dat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 68h arbitration lost in sla+r/w as master; own sla+w has been received, ack returned no s1dat action or no s1dat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 70h general call address (00h) has been received; ack has been returned no s1dat action or no s1dat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 78h arbitration lost in sla+r/w as master; general call address has been received, ack has been returned no s1dat action or no s1dat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 80h previously addressed with own slv address; data has been received; ack has been returned read data byte or read data byte x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 88h previously addressed with own sla; data byte has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to not addressed slv mode; no recognition of own sla or general call address switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free. 90h previously addressed with general call; data byte has been received; ack has been returned read data byte or read data byte x x 0 0 0 0 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 98h previously addressed with general call; data byte has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to not addressed slv mode; no recognition of own sla or general call address switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free.
57 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 table 23 : slave receiver mode (continued) table 24 : slave transmitter mode status status of the application software response code i 2 c bus and to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware sta sto si aa a0h a stop condition or repeated start condition has been received while still addressed as slv/rec or slv/trx no stdat action or no stdat action or no stdat action or no stdat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to not addressed slv mode; no recognition of own sla or general call address switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free. status status of the application software response code i 2 c bus and to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware sta sto si aa a8h own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 0 0 0 1 last data byte will be transmitted and ack bit will be received data byte will be transmitted; ack will be received b0h arbitration lost in sla+r/w as master; own sla+r has been received, ack has been returned load data byte or load data byte x x 0 0 0 0 0 1 last data byte will be transmitted and ack bit will be received data byte will be transmitted; ack bit will be received b8h data byte in s1dat has been transmitted; ack has been received load data byte or load data byte x x 0 0 0 0 0 1 last data byte will be transmitted and ack bit will be received data byte will be transmitted; ack bit will be received c0h data byte in s1dat has been transmitted; not ack has been received no s1dat action or no s1dat action or no s1dat action or no s1dat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to not addressed slv mode; no recognition of own sla or general call address switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free. c8h last data byte in s1dat has been transmitted (aa = 0); ack has been received no s1dat action or no s1dat action or no s1dat action or no s1dat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to not addressed slv mode; no recognition of own sla or general call address switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free.
58 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 slave transmitter mode: in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see figure 23). data transfer is initialized as in the slave receiver mode. when s1adr and s1con have been initialized, sio1 waits until it is addressed by its own slave address followed by the data direction bit which must be 1 (r) for sio1 to operate in the slave transmitter mode. after its own slave address and the r bit have been received, the serial interrupt flag (si) is set and a valid status code can be read from s1sta. this status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in table 24. the slave transmitter mode may also be entered if arbitration is lost while sio1 is in the master mode (see state b0h). if the aa bit is reset during a transfer, sio1 will transmit the last byte of the transfer and enter state c0h or c8h. sio1 is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. thus the master receiver receives all 1s as serial data. while aa is reset, sio1 does not respond to its own slave address or a general call address. however, the i 2 c bus is still monitored, and address recognition may be resumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate sio1 from the i 2 c bus. miscellaneous states: there are two s1sta codes that do not correspond to a defined sio1 hardware state (see table 25). these are discussed below. s1sta = f8h: this status code indicates that no relevant information is available because the serial interrupt flag, si, is not yet set. this occurs between other states and when sio1 is not involved in a serial transfer. s1sta = 00h: this status code indicates that a bus error has occurred during an sio1 serial transfer. a bus error is caused when a start or stop condition occurs at an illegal position in the format frame. examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. a bus error may also be caused when external interference disturbs the internal sio1 signals. when a bus error occurs, si is set. to recover from a bus error, the sto flag must be set and si must be cleared. this causes sio1 to enter the not addre ssed slave mode (a defined state) and to clear the sto flag (no other bits in s1con are affected). the sda and scl lines are released (a stop condition is not transmitted). some special cases: the sio1 hardware has facilities to handle the following special cases that may occur during a serial transfer: simultaneous repeated start conditions from two masters a repeated start condition may be generated in the master transmitter or master receiver modes. a special case occurs if another master simultaneously generates a repeated start condition (see figure 24). until this occurs, arbitration is not lost by either master since they were both transmitting the same data. if the sio1 hardware detects a repeated start condition on the i 2 c bus before generating a repeated start condition itself, it will release the bus, and no interrupt request is generated. if another master frees the bus by generating a stop condition, sio1 will transmit a normal start condition (state 08h), and a retry of the total serial data transfer can commence.
59 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 data transfer after loss of arbitration arbitration may be lost in the master transmitter and master receiver modes (see figure 16). loss of arbitration is indicated by the following states in s1sta; 38h, 68h, 78h, and b0h (see figures 20 and 21). if the sta flag in s1con is set by the routines which service these states, then, if the bus is free again, a start condition (state 08h) is transmitted without intervention by the cpu, and a retry of the total serial transfer can commence. forced access to the i 2 c bus in some applications, it may be possible for an uncontrolled source to cause a bus hang-up. in such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between sda and scl. if an uncontrolled source generates a superfluous start or masks a stop condition, then the i 2 c bus stays busy indefinitely. if the sta flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the i 2 c bus is possible. this is achieved by setting the sto flag while the sta flag is still set. no stop condition is transmitted. the sio1 hardware behaves as if a stop condition was received and is able to transmit a start condition. the sto flag is cleared by hardware. i 2 c bus obstructed by a low level on scl or sda an i 2 c bus hang-up occurs if sda or scl is pulled low by an uncontrolled source. if the scl line is obstructed (pulled low) by a device on the bus, no further serial transfer is possible, and the sio1 hardware cannot resolve this type of problem. when this occurs, the problem must be resolved by the device that is pulling the scl bus line low. if the sda line is obstructed by another device on the bus (e.g., a slave device out of bit synchronization), the problem can be solved by transmitting additional clock pulses on the scl line(see figure 26). the sio1 hardware transmits additional clock pulses when the sta flag is set, but no start condition can be generated because the sda line is pulled low while the i 2 c bus is considered free. the sio1 hardware attempts to generate a start condition after every two additional clock pulses on the scl line. when the sda line is eventually released, a normal start condition is transmitted, state 08h is entered, and the serial transfer continues. if a forced bus access occurs or a repeated start condition is transmitted while sda is obstructed (pulled low), the sio1 hardware performs the same action as described above. in each case, state 08h is entered after a success- ful start condition is transmitted and normal serial transfer continues. note that the cpu is not involved in solving these bus hang-up problems. bus error a bus error occurs when a start or stop condition is present at an illegal position in the format frame. examples of illegal positions are during the serial transfer of an address byte, a data or an acknowledge bit. the sio1 hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. when a bus error is detected, sio1 immediately switches to the not addressed slave mode, releases the sda and scl lines, sets the interrupt flag, and loads the status register with 00h. this status code may be used to vector to a service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in table 25.
60 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 table 25 : miscellaneous states status status of the application software response code i 2 c bus and to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware sta sto si aa f8h no relevant state information available; si = 0 no s1dat action no s1con action wait or proceed current transfer 00h bus error during mst or selected slave modes, due to an illegal start or stop condition. state 00h can also occur when interference causes sio1 to enter an undefined state. no s1dat action 0 1 0 x only the internal hardware is affected in the mst or addressed slv modes. in all cases, the bus is released and sio1 is switched to the not addressed slv mode. sto is reset. figure 24. simultaneous repeated start conditions from 2 masters s 08h sla w a data a s other mst continues p s sla 18h 28h 08h other master sends repeated start condition earlier retry
61 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 sta flag sto flag time limit sda line scl line start condition sta flag start condition (1) unsuccessful attempt to send a start condition (2) sda line released (3) successful attempt to send a start condition; state 08h is entered sda line scl line (1) (1) (2) (3) figure 26. recovering from a bus obstruction caused by a low level on sda figure 25. forced access to a busy i 2 c bus
62 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 flash eprom memory general description the mx10e8050i serial flash memory augments eprom functionality with in-circuit electrical erasure and program- ming. ( mx10e8050i ) the flash can be read and written as bytes. the chip erase operation will erase the entire program memory. the block erase function can erase any flash block. in-system programming and standard parallel programming are both available for mx10e8050i. standard parallel programming is available for mx10e8050i. on- chip erase and write timing generation contribute to a user-friendly programming interface. the mx10e8050i flash reliably stores memory contents even after 100 erase and program cycles. the cell is designed to optimize the erase and programming mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. the mx10e8050i uses a +3.3 v vcc supply to perform the program/erase algorithms. features - flash eprom internal program memory with block erase. - internal 2 k byte fixed boot rom, containing low-level in-system programming routines and a default serial loader. user program can call these routines to perform in-application programming (iap). the boot rom can be turned off to provide access to the full 64 k byte flash memory. ( mx10e8050i/ia ) - boot vector allows user provided flash loader code to reside anywhere in the flash memory space. this configuration provides flexibility to the user. ( mx10e8050i/ia ) - default loader in boot rom allows programming via the serial port without the need for a user provided loader. ( mx10e8050i/ia ) - up to 64 kb external program memory if the internal program memory is disabled ( ea = 0 ). - programming and erase voltage +3.3 v - read/programming/erase: - byte read ( 90 ns access time ). - byte programming ( 50 us typically ). - typical erase times: block erase (16 k bytes ) in 1 second. full erase ( 64 k bytes ) in 4 seconds. - parallel programming with jedec compatible hardware interface to programmer. - in-system programming. - programmable security for the code in the flash. - 100 minimum erase/program cycles for each byte. - 10-year minimum data retention. capabilities of the mx10e8050i flash-based microcontrollers flash organization the mx10e8050i serial contains 64kbytes of flash program memory. this memory is organized as 4 separate blocks. each of the blocks is 16k bytes. figure 28 depicts the flash memory configurations.
63 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 flash programming and erasure mx10e8050i has three methods of erasing or programming of the flash memory that may be used. first, the flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point in the boot rom. the end-user application, though, must be executing code from a different block than the block that is being erased or programmed. second, the on-chip isp boot loader may be invoked. this isp boot loader will, in turn, call low-level routines through the same common entry point in the boot rom that can be used by the end-user application. third, the flash may be programmed or erased using the parallel method by using a commercially available eprom programmer. the parallel programming method used by these devices is similar to that used by eprom 87c51, but it is not identical, and the commercially available programmer will need to have support for these devices. mx10e8050i/ia has parallel programming method of erasing or programming of the flash memory. boot rom ( mx10e8050i ) when the microcontroller programs its own flash memory, all of the low level details are handled by code that is permanently contained in a 2k byte boot rom that is separate from the flash memory. a user program simply calls the common entry point with appropriate parameters in the boot rom to accomplish the desired operation. boot rom operations include things like: erase block, program byte, verify byte, program security lock bit, etc. the boot rom overlays the program memory space at the top of the address space from f800 to ffff hex, when it is enabled. the boot rom may be turned off so that the upper 2k bytes of flash program memory are accessible for execution. fig 28. flash memory configurations ffff c000 8000 4000 0000 block 3 16k bytes 2k bytes block 2 16k bytes block 1 16k bytes block 0 16k bytes program address boot rom ffff fc00 f800 mx10e8050i / ia
64 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 power-on reset code execution the mx10e8050i contains two special flash registers: the boot vector and the status byte. at the falling edge of reset, the mx10e8050i examines the contents of the status byte. if the status byte is set to zero, power-up execution starts at location 0000h, which is the normal start address of the user's application code. when the status byte is set to a value other than zero, the contents of the boot vector is used as the high byte of the execution address and the low byte is set to 00h. the factory default setting is 0fch, corresponds to the address 0fc00h for the factory masked-rom isp boot loader. a custom boot loader can be written with the boot vector set to the custom boot loader. note: when erasing the status byte or boot vector, both bytes are erased at the same time. it is necessary to reprogram the boot vector after erasing and updating the status byte. hardware activation of the boot loader ( mx10e8050i ) the boot loader can also be executed by holding psen low, ea greater than v ih ( such as +3.3 v ), and ale high ( or not connected ) at the falling edge of reset. this is the same effect as having a non-zero status byte. this allows an application to be built that will normally execute the end users code but can be manua lly forced into isp opera- tion. if the factory default setting for the boot vector ( 0fch ) is changed, it will no longer point to the isp masked-rom boot loader code. if this happens, the only way it is possible to change the contents of the boot vector is through the parallel programming method, provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the boot vector and status byte. after programming the flash, the status byte should be programmed to zero in order to allow exe cution of the users application code beginning at address 0000h. fig 29. in-system programming with a minimum of pins + 3.3v +3.3v txd rxd v ss ea v cc txd rxd rst xtal2 xtal1 ale v ss v cc mx10e8050i / ia psen 3.3v
65 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 in-system programming ( isp ) * mx10e8050i : uart the in-system programming (isp) is performed without removing the microcontroller from the system. the in-sys- tem programming (isp) facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the mx10e8050i serial through the serial port. this firmware is provided by mxic and embedded within each mx10e8050i serial device. the mxic in-system programming (isp) facility has made in-circuit programming in an embedded application pos- sible with a minimum of additional expense in components and circuit board area. the isp function uses five pins: txd, rxd, v ss , v cc , and ea. only a small connector needs to be available to interface your application to an external circuit in order to use this feature. the ea supply should be adequately decoupled and ea not allowed to exceed datasheet limits. using the in-system programming ( isp ) ( mx10e8050i ) the isp feature allows for a wide range of baud rates to be used in your application, independent of the oscillator frequency. it is also adaptable to a wide range of oscillator frequencies. this is accomplished by measuring the bit- time of a single bit in a received character. this information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. the isp feature requires that an initial character (an uppercase u) be sent to the mx10e8050i to establish the baud rate. the isp firmware provides auto-echo of received characters. once baud rate initialization has been performed, isp firmware accepts two types record, intel hex record or binary record. intel hex record : intel hex records consist of ascii characters used to represent hexadecimal values and are summarized below: :nnaaaarrdd..ddcc in the intel hex re cord, the nn repre sents the number of data bytes in the record. the mx10e8050i will accept up to 16 (10h) data bytes. the aaaa string repre sents the address of the first byte in the record. if there are zero bytes in the record, this field is often set to 0000. the rr string indicates the record type. a re cord type of 00 is a data record. a record type of 01 indicates the end-of-file mark. in this application, additional record types will be added to indicate either commands or data for the isp facility. the maximum number of data bytes in a record is limited to 16 (decimal). isp commands are summarized in table 26.
66 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 binary record : binary record type same with intel hex record, but need to convert hexadecimal value represented by the ascii character to binary value. a pair of hexadecimal values converts to one binary value. special chara cters dont be changed, eg :, .,u. in the intel hex record, the nn represents the number of data bytes in the record. the 1st n will be converted to the high nibble and the 2nd n will be converted to the low nibble in the binary record. eg 07, binary value in binary record = [07h](1-byte); 07f5, binary value in binary record = [07h][f5h] (2-bytes). example: :01000003 07f5 (13-bytes) full chip erase display of binary value in binary record: : 01 00 00 03 07 f5 [3ah] [01h] [00h] [00h] [03h] [07h] [f5h] (7-bytes) display of binary value of ascii characters in intel hex record: : 0 1 0 0 0 0 0 3 0 7 f 5 [3ah] [30h] [31h] [30h] [30h] [30h] [30h] [30h] [33h] [30h] [37h] [46h] [35h] (13-bytes) where ( binary value of ascii characters ): : = 3ah 0 = 30h 1 = 31h 3 = 33h 5 = 35h 7 = 37h f = 46h as a record is received by the mx10e8050i, the information in the record is stored internally and a checksum calculation is performed. the operation indicated by the record type is not performed until the entire record has been received. should an error occur in the checksum, the mx10e8050i will send an x out the serial port indicating a checksum error. if the checksum calculation is found to match the checksum in the record, then the command will be executed. in most cases, successful reception of the record will be indicated by transm itting a . chara cter out the serial port (displaying the contents of the internal program memory is an exception). in the case of a data record (record type 00), an additional check is made. a . chara cter will not be sent unless the record checksum matched the calculated checksum and all of the bytes in the record were successfully pro- grammed. for a data record, an x indicates that the checksum failed to match, and an r character indicates that one of the bytes did not properly program. winisp, a software utility to implement isp programming with a pc, is available from mxic. commercial serial isp programmers are available from third parties.
67 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 table 26 : command records used by in-system programming record type command/data function 00 program data :nnaaaa00dd....ddcc where: nn = number of bytes (hex) in record aaaa = memory address of first byte in record dd....dd = data bytes cc = checksum example: :10008000af5f67f0602703e0322cfa92007780c3fd 01 end of file (eof), no operation :xxxxxx01cc where: xxxxxx = required field, but value is a dont care cc = checksum example: :00000001ff 02 specify oscillator frequency :01xxxx02ddcc where: xxxx = required field, but value is a dont care dd = integer oscillator frequency rounded down to nearest mhz cc = checksum example: :0100000210ed (dd = 10h = 16, used for 16.0C16.9 mhz)
68 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 record type command/data function 03 miscellaneous write functions :nnxxxx03ffssddcc where: nn = number of bytes (hex) in record xxxx = required field, but value is a dont care 03 = write function ff = subfunction code ss = selection code dd = data input (as needed) cc = checksum subfunction code = 01 (erase blocks) ff = 01 ss = block code as shown below: block 0, 0k to 16k, 00h block 1, 16k to 32k, 40h block 2, 32k to 48k, 80h block 3, 48k to 64k, c0h example: :0200000301c03a erase block 3 subfunction code = 04 (erase boot vector and status byte) ff = 04 ss = dont care example: :020000030400f7 erase boot vector and status byte subfunction code = 05 (program security bits or config bit) ff = 05 ss = 00 program security bit 1 (inhibit writing to flash) 01 program security bit 2 (inhibit flash verify) 02 program security bit 3 (disable external memory) 03 program config bit (6x / 12x clock mode) example: :020000030501f5 program security bit 2 subfunction code = 06 (program status byte or boot vector) ff = 06 ss = 00 program status byte 01 program boot vector example: :030000030601fcf7 program boot vector with 0fch subfunction code = 07 (full chip erase) erases all blocks, security bits, and sets status and boot vector to default values ff = 07 ss = dont care dd = dont care example: :0100000307f5 full chip erase
69 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 record type command/data function 04 display device data or blank check C record type 04 causes the contents of the entire flash array to be sent out the serial port in a formatted display. this display consists of an address and the contents of 16 bytes starting with that address. no display of the device contents will occur if security bit 2 has been programmed. data to the serial port is initiated by the reception of any character and terminated by the reception of any character. general format of function 04 :05xxxx04sssseeeeffcc where: 05 = number of bytes (hex) in record xxxx = required field, but value is a dont care 04 = display device data or blank check function code ssss = starting address eeee = ending address ff = subfunction 00 = display data 01 = blank check cc = checksum example: :0500000440004fff0069 display 4000C4fff 05 miscellaneous read functions general format of function 05 :02xxxx05ffsscc where: 02 = number of bytes (hex) in record xxxx = required field, but value is a dont care 05 = miscellaneous read function code ffss = subfunction and selection code 0700 = read security bits and config bit 0701 = read status byte 0702 = read boot vector cc = checksum example: :020000050701f1 read status byte 06 direct load of baud rate general format of function 06 :02xxxx06hhllcc where: 02 = number of bytes (hex) in record xxxx = required field, but value is a dont care 06 = direct load of baud rate function code hh = high byte of timer 2 ll = low byte of timer 2 cc = checksum example: :02000006f500f3
70 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 * mx10e8050ia : i 2 c the in-system programming ( isp ) is performed without removing the microcontroller from the system. the in- system programming (isp) facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the mx10e8050ia serial through the serial port. this firmware is provided by mxic and embedded within each mx10e8050ia serial device. the mxic in-system programming ( isp ) facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. the isp function uses five pins: sda, scl, vss, vcc, and ea. the ea supply should be adequately decoupled and ea not allowed to exceed datasheet limits. winisp, a software utility to implement isp programming with a pc, is available from mxic. commercial serial isp programmers are available from third parties. winisp is the master and the mx10e8050ia is the slave in isp through i 2 c. the default device address word of mx10e8050ia is 0x26 and the slave address performs on initialization. the slave address can be changed using programmer or calling iap. a write sequence requires some command words, summarized in table 27, following the device address word and acknowledgment. upon receipt of this address, the mx10e8050ia will respond with a zero and then clock in the first 8-bit data word. following receipt of the 8-bit data word, the mx10e8050ia will output a zero. the mx10e8050ia, such as winisp, then must terminate the write sequence with a stop condition. at this time the mx10e8050ia interprets the received command words. the mx10e8050ia will not respond acknowledgment until programming or erasing flashrom is complete. once the programming or erasing has started and the mx10e8050ia inputs are disabled, acknowledge polling can be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if the programming or erasing has completed will the mx10e8050ia respond with a zero, allowing the read or write sequence to continue. a read sequence are initiated the same way as write sequence with the exception that the read/write select bit in the device address word is set to one. a command read requires a " dummy " byte write sequence to load in the command words. once the device address word and command words are clocked in and acknowledged by
71 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005
72 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005
73 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005
74 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 in application progr a mming method ( ia p 4 ) ( m x10e8050i ) several in application programming (iap) calls are available for use by an application program to permit selective erasing and programming of flash sectors. all calls are made throguh a common interface, pgm_mtp. the programming functions are selected by setting up the microcontroller's registers before making a call to pgm_mtp at fff0h. the iap calls are shown in table 28. notes : interrupts and the watchdog timer must be disabled while iap subroutines are executing. rom enable security code register/pdcon (f8h) to execute iap or to enter isp by software setting, this rom enable security code register must be written to 5ah. only when the value of this register is 5ah, user can set enboot bit in auxr1 register. in conclusion, to software enable rom user must write 5ah to pdcon and then set enboot bit in auxr1. example : mov pdcon, #0x5ah orl auxr1, #0x20h bit0 enboot auxr1 (a2h) enboot : this bit determines the bootrom is enabled or disabled. this bit will automatically be set if the status bytes is not zero during reset or entering isp pin setting mode. note this bit is cleared by s/w only. bit2 : bit2 is not writable and alleyways read as a zero. dps : switch between dptr0 and dprt1. dps 0 bit1bit2bit3bit4bit5bit6bit7 remember to turn off rom after executing iap commands. example : anl auxr1, #0xdfh anl pdcon, #0x00h
75 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 iap call pa rameter isp mode check input parameters: r1 = 00h return parameter: acc = 5ah if pass, but acc != 5ah if fail program data byte input parameters: r1 = 02h dptr = address of byte to program acc = byte data to program return parameter: acc = 00 if pass, but acc != 00 if fail erase block input parameters: r1 = 01h dph = block code as shown below: bl ock 0, 0k to 16k, 00h block 1, 16k to 32k, 40h block 2, 32k to 48k, 80h block 3, 48k to 64k, c0h dpl = 00h return parameter: acc = 00 if pass, but acc != 00 if fail erase boot vector input parameters: and status byte r1 = 04h dph = 00h dpl = dont care return parameter: acc = 00 if pass, but acc != 00 if fail program security bit and config bit input parameters: r1 = 05h dph = 00h dpl = 00h C security bit # 1 (inhibit writing to flash) 01h C security bit # 2 (inhibit flash verify) 02h C security bit # 3 (inhibit external memory) 03h C config bit (6/12 clock mode) return parameter: acc = 00 if pass, but acc != 00 if fail program status byte input parameters: r1 = 06h dph = 00h dpl = 00h C program status byte acc = data of status byte return parameter: acc = 00 if pass, but acc != 00 if fail table 28 : iap calls
76 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 program boot vector in put parameters: r1 = 06h dph = 00h dpl = 01h C program boot vector acc = data of boot vector return parameter: acc = 00 if pass, but acc != 00 if fail program i 2 c slave address in put parameters: r1 = 06h dph = 00h dpl = 02h C program i 2 c slave address acc = data of boot vector return parameter: acc = 00 if pass, but acc != 00 if fail read device data input parameters: r1 = 03h dptr = address of byte to read return parameter: acc = value of byte read read security bits and config bit input parameters: r1 = 07h dph= 00h dpl = 00h (security bits) return parameter: acc = value of byte read read status byte input parameters: r1 = 07h dph= 00h dpl = 01h (status byte) return parameter: acc = value of byte read read boot vector input paramet ers: r1 = 07h dph= 00h dpl = 02h (boot vector) return parameter: acc = value of byte read read i 2 c slave address in put parameters: r1 = 07h dph= 00h dpl = 03h (i 2 c slave address) return parameter: acc = value of byte read
77 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 security the security feature protects against software piracy and prevents the contents of the flash from being read. the security lock bits are located in flash. the mx10e8050i serial has 3 programmable security lock bits that will provide different levels of protection for the on-chip code and data ( see table 29 ). security lock bits1 level lb1 lb2 lb3 protection description 1 1 0 0 program and block erase is disabled. erase or programming of the status byte or boot vector is disabled. 2 1 1 0 movc instructions executed from external program memory are disabled from fetching code bytes from internal memory. 3 1 1 1 external execution is disabled. table 29 note : 1. security bits are independent of each other. full-chip erase may be performed regardless of the state of the security bits. 2. any other combination of lock bits is undefined. config : 12-clock or 6-clock mode configuration bit is saved in flash special cell config. the address of config bit is the same as security bits, so do their program or erase algorithm. config bit can be normally programmed but can be erased by chip erased only. defaultly config bit is clear for mx10e8050i serial, that means 12 clock mode. if config bit is programmed to high, 6-clock mode is enabled when reset goes low. note that when programming config to 6-clock mode by isp, the chip would not immediately change to 6-clock mode until another reset going low. mx10e8050i serial is defaultly 6-clock mode.
78 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 lock function table the security bits lock 1~3 could prevent form illegal writing or reading at isp mode or external programming mode. the detail security function table is shown as below: para llel programming lock1 lock2 lock 3 read array x read special cell read id program array x program special cell lock i 2 c address sbyte x bvec x erase array x erase special cell lock x x x i 2 c address sbyte x bvec x chip erase
79 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 absolute maximum ratings parameter rating unit operation temperature 0 to +70 o c storage temperature range - 65 to +150 o c voltage on xtal1, xtal2 pin to v ss v dd +0.5 v maximum i ol per i/o pin 15 ma power dissipation (based on package heat transfer, not device power consumption) 1.5 w notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteristics section of this specification are not implied. 2. this product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid a pplying greater than the rated maximum. 3. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted.
80 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 dc electrical characteristics v dd = 3.0 v to 3.6 v unless otherwise specified; t amb = 0 o c to +70 o c for commercial for industrial unless otherwise specified. symbol parameter test conditions limits unit min typ 1 max i dd power supply current, operating 3.6 v, 40 mhz 11 -1530 ma i id power supply current, idle mode 3.6 v, 40 mhz 11 -1020 ma i pd1 power supply current, 3.0 v 11 -10 ua total power-down mode v ddr vdd rise time - - 2 mv/us v ddf vdd fall time - - 50 mv/us v ram ram keep-alive voltage 1.5 - - v v il input low voltage (ttl input) 2.4 v < v dd < 3.6 v -0.5 - 0.22v dd -0.1 v v ih input high voltage (ttl input) 0.7v dd +0.1 - 5.5 v v ol output low voltage all ports 5, 9 i ol = 20ma; v dd = 2.4 v - - 1.0 v i ol = 3.2ma; v dd = 2.4 v - - 0.3 v v oh output high voltage, all ports 3 i oh =- 20ua; v dd = 2.4 v v dd -0.2 - - v c io input/output pin capacitance 10 --15 pf i ih logical 1 input current, all ports 8 v in = 3.3 v - - -50 ua i li input leakage current, all ports 7 v in = v il or v ih - - 30 ua i tl logical 1-to-0 transition current, v in = 1.5 v at v dd = 3.6 v -30 - -250 ua all ports 3, 6 r rst internal reset pull-up resistor 40 - 225 k ohm notes: 1. typical ratings are not guaranteed. the values listed are at room temperature, 3.3 v. 2. active mode: i cc(max) = 30ma idle mode: i cc(max) = 20ma 3. ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups). does not apply to open drain pins. 4. ports in push-pull mode. does not apply to open drain pins. 5. in all output modes except high impedance mode. 6. port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. this current is highest when v in is approximately 2 v. 7. measured with port in high impedance mode. 8. measured with port in quasi-bidirectional mode. 9. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15 ma maximum total i ol for all outputs: 26 ma maximum total i oh for all outputs: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 10.pin capacitance is characterized but not tested. 11.the i dd and i id specifications are measured using an external clock. this is 12 clock mode.
81 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 icc_vs freq 4mhz 12mhz 20mhz 28mhz 27 24 21 18 15 12 9 6 3 typ idle 40mhz max idle typ active max active icc ( ma )
82 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 low voltage detector ( mx10e8050i / ia ) this low voltage detector will reset the chip when detecting a v dd lower than a designed level. the reset status remains till v dd rise to normal operating voltage. since the reset shall keeps at lease two machine cycle, the v dd low to v dd high shall not transit sooner than two machine cycle. detecting level min max v dd falling 2.40 v 2.60 v v dd rising 2.43 v 2.65 v vdd vdd vfh vfl vrh vrl reset
83 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 ac characteristics (over operating conditions, load capacitance for port 0, ale/prog and psen = 100 pf, load capacitance for all other outputs = 80 pf) tck min. = 1/f max. (maximum operating frequency); tck=clock period symbol parameter 40 mhz, x12 mode unit min max external program memory tlhll ale pulse duration 20 - ns tavll address set-up time to ale 17 - ns tllax add ress hold time after ale 10 - ns tlliv time from ale to valid instruction input - 55 ns tllpl time from ale to control pulse psen 17 - ns tplph control pulse duration psen 70 - ns tpliv time from psen to valid instruction input - 12 ns tpxix input instruction hold time after psen 0 - ns tpxiz input instruction float delay after psen - 20 ns taviv address to valid instruction input - 95 ns tplaz psen low to address float time - 10 ns external data memory tlhll ale pulse duration 20 - ns tavll address set-up time to ale 17 - ns tllax add ress hold time after ale 10 - ns trlrh rd pulse duration 80 - ns twlwh wr pulse duration 80 - ns trldv rd to v alid data input - 60 ns trhdx data hold time after rd 0 - ns trhdz data float delay after rd 32 - ns tlldv time from ale to valid data input - 90 ns tavdv address to valid input - 105 ns tllwl time from ale to rd or wr 40 140 ns tavwl time from address to rd or wr 45 - ns twhlh time from rd or wr high to ale high 10 55 ns tqvwx data valid to wr transition 10 - ns tqvwh data set-up time before wr 125 - ns twhqx data hold time after wr 10 - ns trlaz add ress float delay after rd - 0 ns note: 1. the maximun operating frequency is limited to 40 mhz and the minimum to 3.5 mhz.
84 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 plcc44
85 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 lqfp44
86 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 pdip40
87 p/n:pm0887 mx10e8050i / specifications subject to change without notice, contact your sales representatives for the most update information. preliminary mx10e8050ia rev. 1.6, mar. 28, 2005 revision history revision description page date 1.1 - addition i 2 c pin release jan / 29 / 2003 - pin description release - addition internal data memory sample code release - explain special function registers - boot rom release - isp release 1.2 - addition programming spec. jun / 24 / 2003 - addition i 2 c / uart description 1.3 - update i 2 c, uart function aug / 20 / 2003 - update page 10 symbol ie / ip / iph volume - addition mx10e8050i ( isp + i 2 c ) function - addition oscillator characteristics / reset / idle mode power down mode / design considerations - update reset timing sep / 26 / 2003 1.4 - addition (1:turn off , 0:turn on) 12 mar / 11 / 2004 - addition (fig 29) psen & ale 64 - isp uart part enhance 65 - intel hex --> command (table 26) 67 - table 29 (level 1) lb1&lb2 0 --> 1 77 - addition (ma) 81 - modify flash eprom memory 62 mar / 22 / 2004 - modify fig 29 64 - modify vpp --> ea 65 - modify table 29 level 3 77 1.5 - closed mx10e8050ix-ia jul / 29 / 2004 1.6 - add mx10e8050ia function - modify table 15 , table 16 dec / 03 / 2004 - modify symbol tplaz 83 dec / 21 / 2004 1.6 - modify pwm address 31 mar / 10 / 2005
mx10e8050i / preliminary mx10e8050ia m acronix i nternational c o., l td . headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office : tel:+32-2-456-8020 fax:+32-2-456-8021 hong kong office : tel:+86-755-834-335-79 fax:+86-755-834-380-78 japan office : kawasaki office : tel:+81-44-246-9100 fax:+81-44-246-9105 osaka office : tel:+81-6-4807-5460 fax:+81-6-4807-5461 singapore office : tel:+65-6346-5505 fax:+65-6348-8096 taipei office : tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-262-8887 fax:+1-408-262-8810 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

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